Abstract: An apparatus for testing an integrated circuit includes a clock generator; a first memory for storing at least one instruction data, and a second memory for storing input data and corresponding expected output data employed in testing. A control unit controls the output of the input data and expected output data in accordance with the content of the instruction data. A counter counts clocks output from the generator. A register circuit stores at least one designated value. A comparing circuit outputs at least one control signal based on the comparison between the designed value and a value of the counter. A circuit defining a first timing data, representing a mode of application of a test pattern, and at least one second timing data, representing a mode of application different from the first timing data, outputs one of the first or second timing data in response to the control signal.