Abstract: There is provided a spike noise eliminating circuit that can eliminate reliably spike noise having a predetermined pulse width or smaller and transmit and output precisely a signal having a pulse width larger than the predetermined width. Spike noise in the input signal is eliminated by: detecting a coincidence in level of the input signal and a first delay signal obtained by delaying the input signal by a maximum pulse width of noise to be eliminated as a delay amount; and sampling the input signal or a second delay signal obtained by delaying the input signal by a certain period of time based on a signal obtained as a result of detecting the coincidence in level.

Abstract: There is provided a spike noise eliminating circuit that can eliminate reliably spike noise having a predetermined pulse width or smaller and transmit and output precisely a signal having a pulse width larger than the predetermined width. Spike noise in the input signal is eliminated by: detecting a coincidence in level of the input signal and a first delay signal obtained by delaying the input signal by a maximum pulse width of noise to be eliminated as a delay amount; and sampling the input signal or a second delay signal obtained by delaying the input signal by a certain period of time based on a signal obtained as a result of detecting the coincidence in level.

Abstract: A display panel control circuit includes a voltage controlled oscillator (VCO) for outputting a clock signal, a first-panel horizontal system pulse generation section, a second-panel horizontal system pulse generation section, a vertical system pulse generation section which is commonly used among the first and second panels, a phase comparator, and a smoothing element. The first-panel horizontal system pulse generation section and the second-panel horizontal system pulse generation section respectively generate a reference signal of a first-panel horizontal system output group and a reference signal of a second-panel horizontal system output group from signal VCOCLK1 output from the VCO. Thus, it is possible to simultaneously drive two different panels.

Abstract: A PLL lock detection circuit produces a high precision PLL lock detection signal and enables eliminating a smoothing circuit. The PLL lock detection circuit reliably detects if the PLL circuit is locked reliably and without error by simultaneously evaluating both locked and unlocked states. A continuity detection unit detects if a PLL locked state continues for H consecutive periods, and another continuity detection unit detects if a PLL unlocked state continues for H consecutive periods. The continuity detection units simultaneously output the PLL locked/unlocked states, and an R-S latch holds the detection result.

Abstract: There is provided a vertical frequency distinction circuit and a vertical frequency distinction method capable of reducing a chip area, and a video display apparatus having the vertical frequency distinction circuit. A vertical control pulse generating section of the vertical frequency distinction circuit generates a noise eliminating signal for disabling input of noise during a predetermined period until arrival of a vertical synchronization signal. A distinction result latch section samples the noise eliminating signal and an inversion signal of the noise eliminating signal at the timing of input of the vertical synchronization signal, to generate two output signals. An output selecting section selects either one of the two output signals of the distinction result latch section based on a mode setting signal, to output the selected signal as a distinction result signal.

Abstract: A PLL circuit that makes a voltage-controlled oscillator converge to a stable state within a short time and generates a clock signal with high stability even when discontinuity occurs in the period of a reference input signal is provided. The PLL circuit has a voltage-controlled oscillator for outputting a clock controlled, a first counter reset by the reference input signal having one period longer than a reference period within a predetermined period for outputting a first signal, a second counter for outputting a second signal, a reset pulse generating circuit for resetting the second counter, a loop filter for holding and outputting the control voltage varied by a phase error signal and a discontinuous input detecting part for detecting the reference input signal input initially after its period becomes longer than the reference period.

Abstract: A display panel control circuit includes a voltage controlled oscillator (VCO) for outputting a clock signal, a first-panel horizontal system pulse generation section, a second-panel horizontal system pulse generation section, a vertical system pulse generation section which is commonly used among the first and second panels, a phase comparator, and a smoothing element. The first-panel horizontal system pulse generation section and the second-panel horizontal system pulse generation section respectively generate a reference signal of a first-panel horizontal system output group and a reference signal of a second-panel horizontal system output group from signal VCOCLK1 output from the VCO. Thus, it is possible to simultaneously drive two different panels.

Abstract: The present invention provides a PLL circuit that makes a voltage-controlled oscillator converge to a stable state within a short time and generates a clock signal with high stability even when discontinuity occurs in the period of a reference input signal. The PLL circuit of the present invention has a voltage-controlled oscillator for outputting a clock controlled, a first counter reset by the reference input signal having one period longer than a reference period within a predetermined period for outputting a first signal, a second counter for outputting a second signal, a reset pulse generating circuit for resetting the second counter, a loop filter for holding and outputting the control voltage varied by a phase error signal and a discontinuous input detecting part for detecting the reference input signal input initially after its period becomes longer than the reference period.