Abstract: The microcomputer comprises: a CPU, a DRAM installed within the microcomputer, a non-volatile memory storing a program data therein, an interface commonly used among various circuits within the microcomputer, a system clock generating circuit, which generates clock signals, and is also capable of suspending and regenerating the clock signals, respectively in response to a system clock stop signal and a system clock generation signal, a peripheral circuit which is capable of outputting an interrupt signal requesting the system clock generation to the CPU, and a control circuit which re-transmits the program data from the non-volatile memory to the DRAM in response to a re-initialize request signal output from the CPU, and also outputs an access prohibition, signal for prohibiting the access to the data stored in the DRAM and an access prohibition release signal for releasing the prohibition of access.

Abstract: A semiconductor integrated circuit includes a DRAM memory array to be tested, an algorithmic pattern generator (ALPG), a CPU and an SRAM for the CPU. The ALPG writes data to and reads the data from the DRAM memory array when the operation mode is set at a test mode. Reading the data held in the memory cell when the ALPG writes the data to and reads the data from the memory cell, the CPU locates a defective portion in the DRAM memory array, and analyzes a redundancy section for replacing the defective portion. The SRAM stores the execution code of the operation of the CPU in the test mode, defective decision result and analysis result. The semiconductor integrated circuit can reduce the circuit scale by simplifying the configuration associated with the test function with maintaining the advantages of the real-time test.

Abstract: A DMA control system continuously grants permission to access the I/O device and memory to continue data transfer in a cycle steal mode when there is a continuous stream of DMA requests from a number of I/O devices by producing a logical sum of the DMA requests.

Abstract: A DMA controller interrupts data transfer as needed to transfer the bus use permit to the CPU and resumes data transfer when the CPU completes the memory use in the burst mode in which the predetermined number of words is transferred between the I/O device and the memory.