Patents by Inventor Sachiko Ohuchi

Sachiko Ohuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020080663
    Abstract: An integrate circuit has a first and second logic circuits having common input terminals and the same complementary logic function. The first logic circuit has a pMISFET circuit block and an nMISFET circuit block each with a high threshold value, while the second logic circuit has a pMISFET circuit block and an nMISFET circuit block each with a low threshold value. An output switch circuit intervenes between the pMISFET and nMISFET circuit blocks in each logic circuit and controls the power supply connection to each logic circuit. In operation, the output of the second logic circuit is connected to the output terminal to realize a low power consumption. In the standby state, the output of the first logic circuit is connected to the output terminal to realize a low leakage current.
    Type: Application
    Filed: December 21, 2001
    Publication date: June 27, 2002
    Inventors: Atsushi Kameyama, Tsuneaki Fuse, Masako Yoshida, Kazunori Ohuchi, Sachiko Ohuchi