Abstract: In the memory cell matrix of a semiconductor integrated circuit device having a non-volatile semiconductor memory cell portion and a logic portion, a second-layered Al wires are formed on the first-layered Al wires, with an interlayer insulating film interposed therebetween. The pattern of the second-layered Al wires is the same as that of the first-layered Al wires. This structure reduces the labor for designing mask data, and increases the coating ratio of a resist to an Al layer while minimizing a reduction in the transmittance of ultraviolet ray. As a result, the amount of a reaction compound supplied from the resist into the Al layer for forming the second-layered Al wires increases, which prevents the second-layered Al wires from being undercut. Thus, the second and subsequent-layered Al wires of the logic portion can be effectively prevented from being thinned.