Patents by Inventor Sachiko Shirai

Sachiko Shirai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7956423
    Abstract: A method of a semiconductor device, which includes an insulated-gate FET and an electronic element, includes three steps. The first step is the step of forming a trench gate of the insulated-gate FET in a first region of a semiconductor base and a trench element-isolation layer in a second region of the semiconductor base, simultaneously. The second step is the step of forming a first diffusion layer of the insulated-gate FET on a side of the trench gate and a second diffusion layer of the electronic element in a region surrounded by the trench element-isolation layer, simultaneously. The third step is the step of forming a third diffusion layer of the insulated-gate FET in the first diffusion layer and a fourth diffusion layer of the electronic element in the second diffusion layer, simultaneously.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: June 7, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Takao Arai, Sachiko Shirai, legal representative
  • Publication number: 20090294870
    Abstract: A method of a semiconductor device, which includes an insulated-gate FET and an electronic element, includes three steps. The first step is the step of forming a trench gate of the insulated-gate FET in a first region of a semiconductor base and a trench element-isolation layer in a second region of the semiconductor base, simultaneously. The second step is the step of forming a first diffusion layer of the insulated-gate FET on a side of the trench gate and a second diffusion layer of the electronic element in a region surrounded by the trench element-isolation layer, simultaneously. The third step is the step of forming a third diffusion layer of the insulated-gate FET in the first diffusion layer and a fourth diffusion layer of the electronic element in the second diffusion layer, simultaneously.
    Type: Application
    Filed: May 26, 2009
    Publication date: December 3, 2009
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Takao Arai, Sachiko Shirai