Abstract: A semiconductor device has a transparent dielectric substrate such as a sapphire substrate. To enable fabrication equipment to detect the presence of the substrate optically, the back surface of the substrate is coated with a triple-layer light-reflecting film, preferably a film in which a silicon oxide or silicon nitride layer is sandwiched between polycrystalline silicon layers. This structure provides high reflectance with a combined film thickness of less than half a micrometer.

Abstract: A semiconductor device has a transparent dielectric substrate such as a sapphire substrate. To enable fabrication equipment to detect the presence of the substrate optically, the back surface of the substrate is coated with a triple-layer light-reflecting film, preferably a film in which a silicon oxide or silicon nitride layer is sandwiched between polycrystalline silicon layers. This structure provides high reflectance with a combined film thickness of less than half a micrometer.

Abstract: A semiconductor device has a transparent dielectric substrate such as a sapphire substrate. To enable fabrication equipment to detect the presence of the substrate optically, the back surface of the substrate is coated with a triple-layer light-reflecting film, preferably a film in which a silicon oxide or silicon nitride layer is sandwiched between polycrystalline silicon layers. This structure provides high reflectance with a combined film thickness of less than half a micrometer.

Abstract: A method for manufacturing an electronic device, in which a via hole and a trench for an interconnect are integrally provided in an interlayer insulating film formed on a substrate, and the via hole and the trench for the interconnect are plugged with an electric conductor film is provided. The method includes: forming a via hole in the interlayer insulating film; forming a resin film, plugging the via hole, on the interlayer insulating film; forming a resist mask having an opening for an interconnect on the interlayer insulating film; and etching the interlayer insulating film through an etching mask of the resist mask to form a trench for the interconnect connected with the via hole. The resin film is being capable of trapping a basic substance.

Abstract: A shot of a focus-monitoring mark is provided on a wafer at a first focus position (?DF) defocused from a second focus position (Fk) by a certain amount to measure a dimension (La) of the focus-monitoring mark. The actual focus position (F) of the defocused shot is calculated by the measured dimension (La) and the defocused direction of the defocused shot, using a calibration quadratic function curve (1). The difference (F??DF) between the actual focus position and the defocused amount represents the magnitude and direction of deviation of the actual focus position from the optimum focus position.

Abstract: A semiconductor integrated circuit is fabricated in a substrate having a semiconductor layer and an underlying insulator layer. The fabrication process includes a step of locally oxidizing the semiconductor layer to form a field oxide, during which step the semiconductor layer is protected by a nitride film. The nitride film has both openings to permit local oxidization in the integrated circuit area, and an opening defining an alignment mark adjacent to the circuit area. The alignment mark may be formed either in the semiconductor and insulator layers, or in a part of the nitride film left after the nitride film is removed from the circuit area. In either case, the edge height of the alignment mark is not limited by the thickness of the semiconductor layer. Using the nitride layer to define both the alignment mark and the field oxide reduces the necessary number of fabrication steps.

Abstract: A shot of a focus-monitoring mark is provided on a wafer at a first focus position (?DF) defocused from a second focus position (Fk) by a certain amount to measure a dimension (La) of the focus-monitoring mark. The actual focus position (F) of the defocused shot is calculated by the measured dimension (La) and the defocused direction of the defocused shot, using a calibration quadratic function curve (1). The difference (F??DF) between the actual focus position and the defocused amount represents the magnitude and direction of deviation of the actual focus position from the optimum focus position.

Abstract: A semiconductor device has a transparent dielectric substrate such as a sapphire substrate. To enable fabrication equipment to detect the presence of the substrate optically, the back surface of the substrate is coated with a triple-layer light-reflecting film, preferably a film in which a silicon oxide or silicon nitride layer is sandwiched between polycrystalline silicon layers. This structure provides high reflectance with a combined film thickness of less than half a micrometer.

Abstract: A method for manufacturing an electronic device, in which a via hole and a trench for an interconnect are integrally provided in an interlayer insulating film formed on a substrate, and the via hole and the trench for the interconnect are plugged with an electric conductor film is provided. The method includes: forming a via hole in the interlayer insulating film; forming a resin film, plugging the via hole, on the interlayer insulating film; forming a resist mask having an opening for an interconnect on the interlayer insulating film; and etching the interlayer insulating film through an etching mask of the resist mask to form a trench for the interconnect connected with the via hole. The resin film is being capable of trapping a basic substance.

Abstract: A semiconductor integrated circuit is fabricated in a substrate having a semiconductor layer and an underlying insulator layer. The fabrication process includes a step of locally oxidizing the semiconductor layer to form a field oxide, during which step the semiconductor layer is protected by a nitride film. The nitride film has both openings to permit local oxidization in the integrated circuit area, and an opening defining an alignment mark adjacent to the circuit area. The alignment mark may be formed either in the semiconductor and insulator layers, or in a part of the nitride film left after the nitride film is removed from the circuit area. In either case, the edge height of the alignment mark is not limited by the thickness of the semiconductor layer. Using the nitride layer to define both the alignment mark and the field oxide reduces the necessary number of fabrication steps.

Abstract: A silicon-on-insulator (SOI) substrate has a grid-line region and a circuit region, and includes a silicon substrate having an upper surface, a first insulating layer having an upper surface and a silicon layer, and which has a grid-line region zoning a circuit region. An element isolation region is formed in the silicon layer of the circuit region of the SOI substrate, and an insulating region is formed in the silicon layer of the grid-line region of the SOI substrate. The insulating region and a portion of the first insulating layer located under the insulating region are removed to define a recess in the grid-line region.

Abstract: A photoresist developing nozzle, a photoresist developing apparatus and a photoresist developing method capable of effecting uniform development are provided even in the case of a large diameter wafer. A photoresist nozzle has a plurality of small chambers, developer supply flow passages for supplying developer to respective small chambers, and developer discharge sections for discharging developer supplied from the developer supply flow passages onto the wafer. The photoresist developing apparatus has the photoresist developing nozzle and the photoresist developing method uses the photoresist developing nozzle.

Abstract: A silicon-on-insulator (SOI) substrate having a grid-line region and a circuit region, and including a silicon substrate having an upper surface, a first insulating layer having an upper surface and a silicon layer, and which has a grid-line region zoning a circuit region. An element isolation region is formed in the silicon layer of the circuit region of the SOI substrate, and an insulating region is formed in the silicon layer of the grid-line region of the SOI substrate. The insulating region and a portion of the first insulating layer located under the insulating region are removed to define a recess in the grid-line region.

Abstract: A photoresist developing nozzle, a photoresist developing apparatus and a photoresist developing method capable of effecting uniform development are provided even in the case of a large diameter wafer. A photoresist nozzle is characterized in comprising a nozzle body (8) having a plurality of small chambers (8A to 8E), developer supply flow passages (14A to 14E) for supplying developer to respective small chambers (8A to 8E), developer discharge sections (10) for discharging developer supplied from the developer supply flow passages (14A to 14E) onto the wafer W. The photoresist developing apparatus has the photoresist developing nozzle and the photoresist developing method uses the photoresist developing nozzle.

Abstract: A film thickness distribution measuring method according to the present invention comprises the following steps of measuring a step form lying within a predetermined interval including a substrate exposure region having a coordinate point defined as a measurement reference on a substrate having steps to thereby extract first data L1, forming an organic film over the substrate and thereafter measuring a step form lying within the predetermined interval to thereby extract second data L2, measuring the thickness of the organic film and adding the thickness to the second data L2 to thereby extract third data L3, and determining a difference (L3−L1) between the third data L3 and the first data L1 to thereby measure a continuous film thickness distribution of the organic film formed over the substrate.