Abstract: An interface circuit has a data recovery circuit, a protocol interface circuit and a controller or processor that can be implemented using a finite state machine. The data recovery circuit may be configured to receive a stream of symbols over three wires of a serial bus according to a high-speed mode defined by a Mobile Industry Processor Interface Alliance C-PHY protocol. The protocol interface circuit may be coupled to an output of the data recovery circuit and configured to receive data from the data recovery circuit. The finite state machine may be configured to cause the data recovery circuit to be disabled when an end of transmission is indicated in a first end-of-transmission signal received from the protocol interface circuit.

Abstract: A processing circuit coupled to an imaging device includes a bus interface circuit configured to communicatively couple the processing circuit to the imaging device over a multidrop differential serial link, detector circuits configured to detect a plurality of sequentially occurring signaling states of the multidrop differential serial link, the plurality of sequentially occurring signaling states related to transmissions of data packets over the multidrop differential serial link, and a controller. The controller is configured to discard data packets received after the imaging device is powered on or initialized and until the imaging device is indicated to be in an active operating state, count sequences of transitions between a first signaling state of the multidrop differential serial link and a second signaling state of the multidrop differential serial link, and indicate that the imaging device is in the active operating state after a preconfigured number of data packets have been discarded.

Abstract: A video processing circuit has a bus interface circuit configured to communicatively couple the video processing circuit to an imaging device over a multidrop differential serial link; detector circuits configured to detect sequentially occurring signaling states of the multidrop differential serial link, the sequentially occurring signaling states preceding a transition of the bus interface circuit from a low-power mode to a high-speed mode; and a controller configured to: cause the bus interface circuit to receive data transmitted over the multidrop differential serial link in the high-speed mode when a duration of each signaling state in the sequentially occurring signaling states exceeds a minimum duration defined for the each signaling state; and cause the bus interface circuit to return to the low-power mode when one signaling state of the sequentially occurring signaling states does not exceed a corresponding minimum duration defined for the one signaling state.

Abstract: A communication interface circuit has a shift register configured to convert a serial stream of 3-bit symbols to a parallel multi-symbol word comprising a plurality of symbols ordered in accordance with time of arrival at an input of the shift register; a set of symbol comparators, each symbol comparator being configured to determine whether a pattern of symbols in the parallel multi-symbol word indicates presence of a false synchronization pattern in the serial stream of 3-bit symbols; and a synchronization detection circuit configured to provide a control signal that is active when a synchronization pattern is detected in the serial stream of 3-bit symbols, and further configured to suppress the control signal when at least one of the set of symbol comparators indicates the presence of the false synchronization pattern of 3-bit symbols.