Patents by Inventor Sachin Chopra

Sachin Chopra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210105280
    Abstract: Internet communications between a content management system that stores a plurality of content objects and a third-party system is established. A hierarchy at the third-party system is determined, and a file and folder content object hierarchy at the content management system is generated based on the determined hierarchy at the third-party system. Users of the content management system and users of the third-party system are reconciled by comparing attributes of users of the third-party system with attributes of users of the content management system. Permissions pertaining to user accessed to content objects at the content management system are reconciled with permissions of the third-party system. Reconciled access permissions are applied to content objects of the generated hierarchy at the content management system. Some of the access permissions that are applied to the content object hierarchy of the content management system are more restrictive than the permissions of the third-party system.
    Type: Application
    Filed: October 1, 2020
    Publication date: April 8, 2021
    Applicant: Box, Inc.
    Inventors: Derrik Randal Lansing, Sachin Chopra, Rohit Bakshi, Daniel Wayne Morkovine, Faizan N. Buzdar, Prachi Subhash Jadhav, Yufeng Wu, Sophia Yang, Jerry Luo, Drew Parker
  • Patent number: 6775813
    Abstract: The present invention describes a method and apparatus for placing flops in a complex circuit design. Initially, the method calculates a physical range for every net that requires a flop, within which the flop can be placed satisfying the timing requirement. After the physical range is defined, the method groups these flops and determines a block where these grouped flops can be placed. Grouping these flops into one block (flop station) can preserve a compact layout for the design. The flops are then connected to appropriate nets.
    Type: Grant
    Filed: September 10, 2002
    Date of Patent: August 10, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Sachin Chopra, Yu-Yen Mo, Shyam Sundar, Peter F. Lai, Kong-Fai Woo, Venkat Podduturi, Vishal Chopra
  • Publication number: 20040049756
    Abstract: The present invention describes a method and apparatus for placing flops in a complex circuit design. Initially, the method calculates a physical range for every net that requires a flop, within which the flop can be placed satisfying the timing requirement. After the physical range is defined, the method groups these flops and determines a block where these grouped flops can be placed. Grouping these flops into one block (flop station) can preserve a compact layout for the design. The flops are then connected to appropriate nets.
    Type: Application
    Filed: September 10, 2002
    Publication date: March 11, 2004
    Applicant: Sun Microsystems, Inc.
    Inventors: Sachin Chopra, Yu-Yen Mo, Shyam Sundar, Peter F. Lai, Kong-Fai Woo, Venkat Podduturi, Vishal Chopra
  • Patent number: 6654942
    Abstract: Method and system for providing a netlist driven integrated router in a non-netlist driven environment for microprocessor designs includes retrieving top level netlist for the existing microprocessor design from the top level database and the design parameters for the new microprocessor design, and translating these netlist and design parameters at the front end so that the resulting data can be provided to an integrated router which is configured to generate re-routes for the new microprocessor design based on the top level netlist and the design parameters, where the generated re-routes are provided to a back end for translating the re-routes to new top level netlist and merging the new top level netlist with the existing top level netlist database.
    Type: Grant
    Filed: August 22, 2001
    Date of Patent: November 25, 2003
    Assignee: Sun Microsystems, Inc.
    Inventors: Sachin Chopra, Peter Fu, Kong-Fal Woo, Peter Lai, Srirarm Satakopan, Hsiu-Nien Chen, Von-Kyoung Kim, Yongjun Zhang
  • Patent number: 6581200
    Abstract: A method of designing an integrated circuit, by generating a first netlist for a first router design tool, abstracting the first netlist to mask selected old routes, and generating a second netlist for a second router design tool using new routing information which excludes the masked old routes. In an exemplary use, the first routing tool is an older tool, while the second routing tool is a newer tool that can provide a more compact database and more efficient routing. The first routing tool may use a format (e.g., ASCII) which is different from the format used by the second router design tool (e.g., binary). In such a case, the channel abstraction may involve extracting all channel routes from the first format, and converting the extracted channel routes into the second format. New routes can be established using the second router design tool based on the second netlist, while preserving other old routes.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: June 17, 2003
    Assignee: Sun Microsystems, Inc.
    Inventors: Sachin Chopra, Kong-Fai Wo
  • Publication number: 20030041309
    Abstract: A method of designing an integrated circuit, by generating a first netlist for a first router design tool, abstracting the first netlist to mask selected old routes, and generating a second netlist for a second router design tool using new routing information which excludes the masked old routes. In an exemplary use, the first routing tool is an older tool, while the second routing tool is a newer tool that can provide a more compact database and more efficient routing. The first routing tool may use a format (e.g., ASCII) which is different from the format used by the second router design tool (e.g., binary). In such a case, the channel abstraction may involve extracting all channel routes from the first format, and converting the extracted channel routes into the second format. New routes can be established using the second router design tool based on the second netlist, while preserving other old routes.
    Type: Application
    Filed: August 17, 2001
    Publication date: February 27, 2003
    Applicant: Sun Microsystems, Inc.
    Inventors: Sachin Chopra, Kong-Fai Wo
  • Publication number: 20030041310
    Abstract: Method and system for providing a netlist driven integrated router in a non-netlist driven environment for microprocessor designs includes retrieving top level netlist for the existing microprocessor design from the top level database and the design parameters for the new microprocessor design, and translating these netlist and design parameters at the front end so that the resulting data can be provided to an integrated router which is configured to generate re-routes for the new microprocessor design based on the top level netlist and the design parameters, where the generated re-routes are provided to a back end for translating the re-routes to new top level netlist and merging the new top level netlist with the existing top level netlist database.
    Type: Application
    Filed: August 22, 2001
    Publication date: February 27, 2003
    Inventors: Sachin Chopra, Peter Fu, Kong-Fai Woo, Peter Lai, Srirarm Satakopan, Hsiu-Nien Chen, Von-Kyoung Kim, Yongjun Zhang