Abstract: Embodiments of present disclosure relates to and systems to reduce propagation delays in hardware implementation of 3GPP confidentiality or standardized algorithm 128-EEA3 and 3GPP integrity algorithm 128-EIA3 using ZUC module. The reduction of the propagation delays is achieved by improving or optimizing secondary critical paths, which are subsequent to primary critical path, related to the 3GPP confidentiality or standardized algorithm 128-EEA3 and the 3GPP integrity algorithm 128-EIA3. Non-conventional modifications in the hardware implementation are proposed for the improvement or optimization.

Abstract: Embodiments of present disclosure relates to and systems to reduce propagation delays in hardware implementation of 3GPP confidentiality or standardized algorithm 128-EEA3 and 3GPP integrity algorithm 128-EIA3 using ZUC module. The reduction of the propagation delays is achieved by improving or optimizing secondary critical paths, which are subsequent to primary critical path, related to the 3GPP confidentiality or standardized algorithm 128-EEA3 and the 3GPP integrity algorithm 128-EIA3. Non-conventional modifications in the hardware implementation are proposed for the improvement or optimization.

Abstract: A system and method for providing multi-processor data plane architecture have been provided. The method comprises selecting several processing units for performing an egress data process and an ingress data process. A number of processing units are selected for performing an egress data process based on a type of switch and data rate. Several processing pipes are provided for each processing unit. Each processing pipe is divided into several processing stages based on a number of lookup tables used in the egress data process and the ingress data process to absorb a response time of a memory device. The data is stored in several databases in each processing unit, and the databases are copied into several banks to increase an access time with a storage device, such as DDR-SDRAM. Several headers are resynchronized using a fixed delay time through an ACL unit.

Abstract: A system and method for providing multi-processor data plane architecture have been provided. The method comprises selecting several processing units for performing an egress data process and an ingress data process. A number of processing units are selected for performing an egress data process based on a type of switch and data rate. Several processing pipes are provided for each processing unit. Each processing pipe is divided into several processing stages based on a number of lookup tables used in the egress data process and the ingress data process to absorb a response time of a memory device. The data is stored in several databases in each processing unit, and the databases are copied into several banks to increase an access time with a storage device, such as DDR-SDRAM. Several headers are resynchronized using a fixed delay time through an ACL unit.