Patents by Inventor Sachin Mathur
Sachin Mathur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20200212915Abstract: A phase alignment system for aligning clocks is disclosed. The system includes a calibration circuit and a phase locked loop (PLL). The calibration circuit is configured to receive a variable clock and a reference clock; determine phase alignment based on metastability; determine phase misalignment and generate a phase shift upon determining phase misalignment. The PLL is configured to generate the variable clock and incorporate the phase shift.Type: ApplicationFiled: December 27, 2018Publication date: July 2, 2020Inventors: Ravindar Attineni, Sachin Mathur, Jiaxiang Shi
-
Patent number: 10700687Abstract: A phase alignment system for aligning clocks is disclosed. The system includes a calibration circuit and a phase locked loop (PLL). The calibration circuit is configured to receive a variable clock and a reference clock; determine phase alignment based on metastability; determine phase misalignment and generate a phase shift upon determining phase misalignment. The PLL is configured to generate the variable clock and incorporate the phase shift.Type: GrantFiled: December 27, 2018Date of Patent: June 30, 2020Assignee: Intel CorporationInventors: Ravindar Attineni, Sachin Mathur, Jiaxiang Shi
-
Patent number: 8560999Abstract: A method for designing an electronic circuit including determining at least one hold violation in a net routing; inserting a routing blockage associated with each at least one hold violation; de-routing the determined net-routing and re-routing the determined net-routing dependent on at least the routing blockage.Type: GrantFiled: December 30, 2010Date of Patent: October 15, 2013Assignee: STMicroelectronics International N. V.Inventor: Sachin Mathur
-
Publication number: 20120174052Abstract: A method for designing an electronic circuit including determining at least one hold violation in a net routing; inserting a routing blockage associated with each at least one hold violation; de-routing the determined net-routing and re-routing the determined net-routing dependent on at least the routing blockage.Type: ApplicationFiled: December 30, 2010Publication date: July 5, 2012Applicant: STMicroelectronics Pvt. Ltd.Inventor: Sachin Mathur
-
Patent number: 8086767Abstract: A semiconductor device coupled to input/output pins includes a first core to operate a first function and a second core to operate a second function. A multiplexer is arranged to set the input/output pins to the first function or to the second function, and an arbiter is configured to receive requests from the cores to use the input/output pins and to grant use of the input/output pins to a selected core. A register is arranged to store a value indicative of a delay to be applied by the arbiter when granting use of the input/output pins to the second core.Type: GrantFiled: May 6, 2011Date of Patent: December 27, 2011Assignee: Lantiq Deutschland GmbHInventors: Alvin Lim, Balakrishnan Kangol, Sreekumar Padmanabhan, Sachin Mathur
-
Publication number: 20110213903Abstract: A semiconductor device coupled to input/output pins includes a first core to operate a first function and a second core to operate a second function. A multiplexer is arranged to set the input/output pins to the first function or to the second function, and an arbiter is configured to receive requests from the cores to use the input/output pins and to grant use of the input/output pins to a selected core. A register is arranged to store a value indicative of a delay to be applied by the arbiter when granting use of the input/output pins to the second core.Type: ApplicationFiled: May 6, 2011Publication date: September 1, 2011Inventors: Alvin Lim, Balakrishnan Kangol, Sreekumar Padmanabhan, Sachin Mathur
-
Patent number: 7962670Abstract: A semiconductor device coupled to input/output pins includes a first core to operate a first function and a second core to operate a second function. A multiplexer is arranged to set the input/output pins to the first function or to the second function, and an arbiter is configured to receive requests from the cores to use the input/output pins and to grant use of the input/output pins to a selected core. A register is arranged to store a value indicative of a delay to be applied by the arbiter when granting use of the input/output pins to the second core.Type: GrantFiled: June 6, 2007Date of Patent: June 14, 2011Assignee: Lantiq Deutschland GmbHInventors: Alvin Lim, Balakrishnan Kangol, Sreekumar Padmanabhan, Sachin Mathur
-
Patent number: 7613213Abstract: Time multiplexed processing of multiple SONET signals uses the same shared circuitry for framing, descrambling, maintenance signal processing, control byte processing and extraction, pointer tracking, retiming, and alarm indication. The signals are deserialized and multiplexed onto a byte-wide bus from which they are processed in a shared pipeline. Additional pipelines allow scaling up to higher capacity SONET signals. Each pipeline is provided with means for communicating with the other pipelines so that information derived from the processing of one stream can be shared with the processing of other streams when necessary. According to the presently preferred embodiment, bytes pass through the pipeline in five clock cycles.Type: GrantFiled: August 23, 2005Date of Patent: November 3, 2009Assignee: Transwitch CorporationInventors: Pushkal Yadav, Kumar Shakti Singh, Chitra Wadhwa, Sachin Mathur, Ashis Maitra, Amandeep Singh Gujral, Diljit Singh, Yudhishthira Kundu
-
Publication number: 20080304351Abstract: A semiconductor device coupled to input/output pins includes a first core to operate a first function and a second core to operate a second function. A multiplexer is arranged to set the input/output pins to the first function or to the second function, and an arbiter is configured to receive requests from the cores to use the input/output pins and to grant use of the input/output pins to a selected core. A register is arranged to store a value indicative of a delay to be applied by the arbiter when granting use of the input/output pins to the second core.Type: ApplicationFiled: June 6, 2007Publication date: December 11, 2008Inventors: Alvin Lim, Balakrishnan Kangol, Sreekumar Padmanabhan, Sachin Mathur
-
Patent number: 7349444Abstract: Methods for retiming SONET signals include demultiplexing STS-1 signals from an STS-N signal, buffering each of the STS-1 signals in a FIFO, determining the FIFO depth over time, and determining a pointer leak rate based in part on FIFO depth and also based on the rate of received pointer movements. According to the presently preferred embodiment, each FIFO is 29 bytes deep. If FIFO depth is 12-17 bytes, no leaking is performed. If the depth is 8-12 bytes or 17-21 bytes, a slow leak rate is set. If the depth is 4-8 bytes or 21-25 bytes, a fast leak rate is set. If the depth is 0-4 bytes or 25-29 bytes, pointer movements are immediate. The calculated leak rates are based on the net number of pointer movements (magnitude of positive and negative movements summed) received during a sliding window of n×32 seconds (n×256,000 frames).Type: GrantFiled: August 23, 2004Date of Patent: March 25, 2008Assignee: Transwitch CorporationInventors: Daniel C. Upp, Suvhasis Mukhopadhyay, Bart Brosens, Kris Van Aken, Chitra Wadhwa, Sachin Mathur, Ramses Valvekens
-
Publication number: 20060039415Abstract: Methods for retiming SONET signals include demultiplexing STS-1 signals from an STS-N signal, buffering each of the STS-1 signals in a FIFO, determining the FIFO depth over time, and determining a pointer leak rate based in part on FIFO depth and also based on the rate of received pointer movements. According to the presently preferred embodiment, each FIFO is 29 bytes deep. If FIFO depth is 12-17 bytes, no leaking is performed. If the depth is 8-12 bytes or 17-21 bytes, a slow leak rate is set. If the depth is 4-8 bytes or 21-25 bytes, a fast leak rate is set. If the depth is 0-4 bytes or 25-29 bytes, pointer movements are immediate. The calculated leak rates are based on the net number of pointer movements (magnitude of positive and negative movements summed) received during a sliding window of n×32 seconds (n×256,000 frames).Type: ApplicationFiled: August 23, 2004Publication date: February 23, 2006Inventors: Daniel Upp, Suvhasis Mukhopadhyay, Bart Brosens, Kris Aken, Chitra Wadhwa, Sachin Mathur, Ramses Valvekens
-
Publication number: 20060039416Abstract: Time multiplexed processing of multiple SONET signals uses the same shared circuitry for framing, descrambling, maintenance signal processing, control byte processing and extraction, pointer tracking, retiming, and alarm indication. The signals are deserialized and multiplexed onto a byte-wide bus from which they are processed in a shared pipeline. Additional pipelines allow scaling up to higher capacity SONET signals. Each pipeline is provided with means for communicating with the other pipelines so that information derived from the processing of one stream can be shared with the processing of other streams when necessary. According to the presently preferred embodiment, bytes pass through the pipeline in five clock cycles.Type: ApplicationFiled: August 23, 2005Publication date: February 23, 2006Inventors: Pushkal Yadav, Kumar Singh, Chitra Wadhwa, Sachin Mathur, Ashis Maitra, Amandeep Gujral, Diljit Singh