Patents by Inventor Sachin P. Ghanekar

Sachin P. Ghanekar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11669725
    Abstract: Using a buffer sized according to the size of the filters of a convolutional neural network (CNN), a processor may use a read pointer to generate a two-dimensional virtual matrix of inputs. The number of inputs in each row in the two-dimensional virtual matrix of inputs may match the one-dimensional filter size of the cubic filters. The processor may collapse each of the cubic filters to one-dimensional linear arrays and generate a two-dimensional filter matrix from the one-dimensional linear arrays. The convolution computations for a corresponding layer of the CNN therefore reduce to a single matrix multiplication without any memory movement operations. When the buffer is refreshed using a new input frame, the processor may increment the initial read address of each read pointer by one and increment the final read address by one, circling back to the corresponding initial read address.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: June 6, 2023
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ananda Sarangaram Tharma Ranga Raja, Prasad Nikam, N D Divyakumar, Himanshu Singhal, Vijay Pawar, Sachin P. Ghanekar
  • Patent number: 10379813
    Abstract: Embodiments may include receiving an input block of data having one or more rows wherein each row includes one or more elements. Embodiments may further include adjusting the input block of data to generate a two-dimensional sorted block of data and identifying at least one position within the two-dimensional sorted block of data that cannot contain a median value or a desired Nth sorted value. Embodiments may also include sorting the two-dimensional block of data along one or more columns to obtain one or more candidate elements that contain the median value or the desired Nth sorted value. Embodiments may include discarding at least one non-candidate element to generate one or more remaining elements and rearranging the one or more remaining elements such that a number of diagonal elements form a column. Embodiments may also include iteratively repeating some of the above operations until a desired value is identified.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: August 13, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Sachin P. Ghanekar, Pavan Shridhar Jalwadi
  • Patent number: 9117060
    Abstract: A system and method for preventing an application program, which is licensed to a customer to be exclusively executed in a processor based on a certain processor design, from being executed properly in unauthorized processors is provided. The system includes a scrambling module and a recovery module. The scrambling module scrambles a selected portion of the application program using an identifier which identifies the authorized processor design. The recovery module adds an unscrambling program to the application program such that when the program is running in a processor, it retrieves a second identifier from the processor and unscrambles the scrambled portion of the application program using the retrieved second identifier. If the second identifier does not correspond to an authorized processor design, the unscrambling operation will incorrectly unscramble the scrambled portion and the application program will not run properly.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: August 25, 2015
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Darin S. Petkov, Dror E. Maydan, Pushkar G. Patwardhan, Sachin P. Ghanekar, Samir S. Pathak
  • Publication number: 20100287622
    Abstract: A system and method for preventing an application program, which is licensed to a customer to be exclusively executed in a processor based on a certain processor design, from being executed properly in unauthorized processors is provided. The system includes a scrambling module and a recovery module. The scrambling module scrambles a selected portion of the application program using an identifier which identifies the authorized processor design. The recovery module adds an unscrambling program to the application program such that when the program is running in a processor, it retrieves a second identifier from the processor and unscrambles the scrambled portion of the application program using the retrieved second identifier. If the second identifier does not correspond to an authorized processor design, the unscrambling operation will incorrectly unscramble the scrambled portion and the application program will not run properly.
    Type: Application
    Filed: May 7, 2009
    Publication date: November 11, 2010
    Inventors: Darin S. Petkov, Dror E. Maydan, Pushkar G. Patwardhan, Sachin P. Ghanekar, Samir S. Pathak
  • Patent number: 7668715
    Abstract: A method of performing quantization in an audio encoder includes determining a number of bits available in a frame of encoded audio data. Determinations are also made for the maximum transform coefficient value and a distribution of transform coefficient values across the transform coefficient spectrum being encoded. A an estimate for an initial quantization step value is determined from the number of available bits in the frame, the maximum transform coefficient value, and the distribution of coefficient values across the coefficient spectrum.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: February 23, 2010
    Assignee: Cirrus Logic, Inc.
    Inventors: Ravindra Ramkrishna Chaugule, Sachin P. Ghanekar