Patents by Inventor Sachin Prabhakarrao KADU
Sachin Prabhakarrao KADU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11948653Abstract: A semiconductor chip with error detection and correction includes multiple pipes and each pipe is coupled to one or more ports on the semiconductor chip. The semiconductor chip further includes a state machine coupled to the pipes to generate a number of events consisting of read- and/or scan-type events associated with a plurality of storage elements. The state machine is implemented in hardware and can centrally detect and correct erroneous memory entries across the plurality of storage elements.Type: GrantFiled: July 20, 2021Date of Patent: April 2, 2024Assignee: Avago Technologies International Sales Pte. LimitedInventor: Sachin Prabhakarrao Kadu
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Patent number: 11949586Abstract: A semiconductor chip for implementing load-aware equal-cost multipath routing includes a number of ports and several pipes, each pipe being coupled to a portion of ports on the semiconductor chip, and a central unit consisting of a state machine and multiple databases. The databases contain information regarding a communication network including an overlay network and an underlay network, and the state machine is implemented in hardware and can determine at least one feature of the overlay network and a corresponding group of paths within the underlay network.Type: GrantFiled: April 20, 2023Date of Patent: April 2, 2024Assignee: Avago Technologies International Sales Pte. LimitedInventor: Sachin Prabhakarrao Kadu
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Patent number: 11909670Abstract: The disclosed systems and methods provide methods and systems for providing power throttling adapted for high performance network switches. A method includes determining, for each of a plurality of measurement periods within a thermal average period, an energy usage estimate for a packet processing block configured to process ingress packets at a power gated clock rate. The method includes determining, for each of the plurality of measurement periods, a target clock rate for the packet processing block based on the determined energy usage estimates to meet a target energy value that is averaged for the thermal average period. The method includes adjusting, for each of the plurality of measurement periods, the power gated clock rate towards the target clock rate, wherein the adjusting causes the packet processing block to process the ingress packets at the adjusted power gated clock rate.Type: GrantFiled: June 21, 2022Date of Patent: February 20, 2024Assignee: Avago Technologies International Sales Pte. LimitedInventors: Surendra Anubolu, Sachin Prabhakarrao Kadu, Laxminarasimha Rao Kesiraju, Mohan V. Kalkunte
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Publication number: 20230412515Abstract: A semiconductor chip for implementing aggregated flow detection and management includes a number of pipes, where each pipe is coupled to a portion of ports on the semiconductor chip that are to receive data packets. A logic is coupled to the pipes and is used to detect and manage an elephant flow. The elephant flow-detection and management logic includes a flow table and a byte counter.Type: ApplicationFiled: August 28, 2023Publication date: December 21, 2023Applicant: Avago Technologies International Sales Pte. LimitedInventor: Sachin Prabhakarrao Kadu
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Publication number: 20230396560Abstract: Disclosed herein are related to systems and methods for scheduling network operations with synchronized idle slots. In one aspect, a system includes a first data path to provide a first set of packets and a second data path to provide a second set of packets. The system also includes an arbiter to arbitrate the first set of packets and the second set of packets. The arbiter may be configured to receive a request for a task, where the task may be performed during a clock cycle. Based on the request, the arbiter may cause a scheduler to schedule a first idle slot for the first data path, and schedule a second idle slot for the second data path. The arbiter may provide the first idle slot and the second idle slot.Type: ApplicationFiled: August 11, 2023Publication date: December 7, 2023Applicant: Avago Technologies International Sales Pte. LimitedInventor: Sachin Prabhakarrao Kadu
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Patent number: 11784935Abstract: A semiconductor chip for implementing aggregated flow detection and management includes a number of pipes, where each pipe is coupled to a portion of ports on the semiconductor chip that are to receive data packets. A logic is coupled to the pipes and is used to detect and manage an elephant flow. The elephant flow-detection and management logic includes a flow table and a byte counter.Type: GrantFiled: September 14, 2021Date of Patent: October 10, 2023Assignee: Avago Technologies International Sales Pte. LimitedInventor: Sachin Prabhakarrao Kadu
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Patent number: 11765097Abstract: Disclosed herein are related to systems and methods for scheduling network operations with synchronized idle slots. In one aspect, a system includes a first data path to provide a first set of packets and a second data path to provide a second set of packets. The system also includes an arbiter to arbitrate the first set of packets and the second set of packets. The arbiter may be configured to receive a request for a task, where the task may be performed during a clock cycle. Based on the request, the arbiter may cause a scheduler to schedule a first idle slot for the first data path, and schedule a second idle slot for the second data path. The arbiter may provide the first idle slot and the second idle slot.Type: GrantFiled: January 28, 2022Date of Patent: September 19, 2023Assignee: Avago Technologies International Sales Pte. LimitedInventor: Sachin Prabhakarrao Kadu
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Publication number: 20230246978Abstract: Disclosed herein are related to systems and methods for scheduling network operations with synchronized idle slots. In one aspect, a system includes a first data path to provide a first set of packets and a second data path to provide a second set of packets. The system also includes an arbiter to arbitrate the first set of packets and the second set of packets. The arbiter may be configured to receive a request for a task, where the task may be performed during a clock cycle. Based on the request, the arbiter may cause a scheduler to schedule a first idle slot for the first data path, and schedule a second idle slot for the second data path. The arbiter may provide the first idle slot and the second idle slot.Type: ApplicationFiled: January 28, 2022Publication date: August 3, 2023Inventor: Sachin Prabhakarrao Kadu
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Patent number: 11683261Abstract: A semiconductor chip for implementing load-aware equal-cost multipath routing includes a number of ports and several pipes, each pipe being coupled to a portion of ports on the semiconductor chip, and a central unit consisting of a state machine and multiple databases. The databases contain information regarding a communication network including an overlay network and an underlay network, and the state machine is implemented in hardware and can determine at least one feature of the overlay network and a corresponding group of paths within the underlay network.Type: GrantFiled: November 30, 2021Date of Patent: June 20, 2023Assignee: Avago Technologies International Sales Pte. LimitedInventor: Sachin Prabhakarrao Kadu
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Publication number: 20230079762Abstract: A semiconductor chip for implementing aggregated flow detection and management includes a number of pipes, where each pipe is coupled to a portion of ports on the semiconductor chip that are to receive data packets. A logic is coupled to the pipes and is used to detect and manage an elephant flow. The elephant flow-detection and management logic includes a flow table and a byte counter.Type: ApplicationFiled: September 14, 2021Publication date: March 16, 2023Inventor: Sachin Prabhakarrao KADU
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Patent number: 11575457Abstract: A method for power-smart packet processing includes, in response to an event trigger signal, generating, by a state machine, a number of enable signals. The method further includes applying the enable signals to a number of single-level inferred clock (SLICK) gates to generate multiple clock signals with cycles of latency. The clock signals are applied to at least some of a number of groups of flops used for packet processing. The enable signals are clock-gated enable signals that start at consecutive cycles of a main clock, and stay active for at least one cycle of the main clock. The method further includes using flow-aware clock-gating technology (FACT) to distinctly identify logic and tables and continually variable traffic (CVT) to control packet rate and packet spacing.Type: GrantFiled: January 19, 2021Date of Patent: February 7, 2023Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDInventor: Sachin Prabhakarrao Kadu
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Publication number: 20230027273Abstract: A semiconductor chip with error detection and correction includes multiple pipes and each pipe is coupled to one or more ports on the semiconductor chip. The semiconductor chip further includes a state machine coupled to the pipes to generate a number of events consisting of read- and/or scan-type events associated with a plurality of storage elements. The state machine is implemented in hardware and can centrally detect and correct erroneous memory entries across the plurality of storage elements.Type: ApplicationFiled: July 20, 2021Publication date: January 26, 2023Inventor: Sachin Prabhakarrao KADU
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Patent number: 11558289Abstract: The disclosed systems and methods provide hyperscalar packet processing. A method includes receiving a plurality of network packets from a plurality of data paths. The method also includes arbitrating, based at least in part on an arbitration policy, the plurality of network packets to a plurality of packet processing blocks comprising one or more full processing blocks and one or more limited processing blocks. The method also includes processing, in parallel, the plurality of network packets via the plurality of packet processing blocks, wherein each of the one or more full processing blocks processes a first quantity of network packets during a clock cycle, and wherein each of the one or more limited processing blocks processes a second quantity of network packets during the clock cycle that is greater than the first quantity of network packets. The method also includes sending the processed network packets through data buses.Type: GrantFiled: October 22, 2021Date of Patent: January 17, 2023Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDInventor: Sachin Prabhakarrao Kadu
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Publication number: 20220337511Abstract: A semiconductor chip for implementing load-aware equal-cost multipath routing includes a number of ports and several pipes, each pipe being coupled to a portion of ports on the semiconductor chip, and a central unit consisting of a state machine and multiple databases. The databases contain information regarding a communication network including an overlay network and an underlay network, and the state machine is implemented in hardware and can determine at least one feature of the overlay network and a corresponding group of paths within the underlay network.Type: ApplicationFiled: November 30, 2021Publication date: October 20, 2022Inventor: Sachin Prabhakarrao KADU
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Publication number: 20220321504Abstract: The disclosed systems and methods provide methods and systems for providing power throttling adapted for high performance network switches. A method includes determining, for each of a plurality of measurement periods within a thermal average period, an energy usage estimate for a packet processing block configured to process ingress packets at a power gated clock rate. The method includes determining, for each of the plurality of measurement periods, a target clock rate for the packet processing block based on the determined energy usage estimates to meet a target energy value that is averaged for the thermal average period. The method includes adjusting, for each of the plurality of measurement periods, the power gated clock rate towards the target clock rate, wherein the adjusting causes the packet processing block to process the ingress packets at the adjusted power gated clock rate.Type: ApplicationFiled: June 21, 2022Publication date: October 6, 2022Inventors: Surendra ANUBOLU, Sachin Prabhakarrao KADU, Laxminarasimha Rao KESIRAJU, Mohan V. KALKUNTE
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Publication number: 20220231776Abstract: A method for power-smart packet processing includes, in response to an event trigger signal, generating, by a state machine, a number of enable signals. The method further includes applying the enable signals to a number of single-level inferred clock (SLICK) gates to generate multiple clock signals with cycles of latency. The clock signals are applied to at least some of a number of groups of flops used for packet processing. The enable signals are clock-gated enable signals that start at consecutive cycles of a main clock, and stay active for at least one cycle of the main clock. The method further includes using flow-aware clock-gating technology (FACT) to distinctly identify logic and tables and continually variable traffic (CVT) to control packet rate and packet spacing.Type: ApplicationFiled: January 19, 2021Publication date: July 21, 2022Inventor: Sachin Prabhakarrao KADU
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Patent number: 11368412Abstract: The disclosed systems and methods provide methods and systems for providing power throttling adapted for high performance network switches. A method includes determining, for each of a plurality of measurement periods within a thermal average period, an energy usage estimate for a packet processing block configured to process ingress packets at a power gated clock rate. The method includes determining, for each of the plurality of measurement periods, a target clock rate for the packet processing block based on the determined energy usage estimates to meet a target energy value that is averaged for the thermal average period. The method includes adjusting, for each of the plurality of measurement periods, the power gated clock rate towards the target clock rate, wherein the adjusting causes the packet processing block to process the ingress packets at the adjusted power gated clock rate.Type: GrantFiled: July 31, 2020Date of Patent: June 21, 2022Assignee: Avago Technologies International Sales Pte. LimitedInventors: Surendra Anubolu, Sachin Prabhakarrao Kadu, Laxminarasimha Rao Kesiraju, Mohan V. Kalkunte
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Patent number: 11323358Abstract: A semiconductor chip for implementing load-aware equal-cost multipath routing includes a number of pipes, each pipe being coupled to a portion of ports on the semiconductor chip, and a central unit consisting of a state machine and multiple databases. The databases contain information regarding a communication network including an overlay network and an underlay network, and the state machine is implemented in hardware and can optimize at least one feature of the overlay network and a corresponding group of paths within the underlay network.Type: GrantFiled: April 14, 2021Date of Patent: May 3, 2022Assignee: Avago Technologies International Sales Pte. LimitedInventor: Sachin Prabhakarrao Kadu
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Publication number: 20220045942Abstract: The disclosed systems and methods provide hyperscalar packet processing. A method includes receiving a plurality of network packets from a plurality of data paths. The method also includes arbitrating, based at least in part on an arbitration policy, the plurality of network packets to a plurality of packet processing blocks comprising one or more full processing blocks and one or more limited processing blocks. The method also includes processing, in parallel, the plurality of network packets via the plurality of packet processing blocks, wherein each of the one or more full processing blocks processes a first quantity of network packets during a clock cycle, and wherein each of the one or more limited processing blocks processes a second quantity of network packets during the clock cycle that is greater than the first quantity of network packets. The method also includes sending the processed network packets through data buses.Type: ApplicationFiled: October 22, 2021Publication date: February 10, 2022Inventor: Sachin Prabhakarrao Kadu
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Publication number: 20220038394Abstract: The disclosed systems and methods provide methods and systems for providing power throttling adapted for high performance network switches. A method includes determining, for each of a plurality of measurement periods within a thermal average period, an energy usage estimate for a packet processing block configured to process ingress packets at a power gated clock rate. The method includes determining, for each of the plurality of measurement periods, a target clock rate for the packet processing block based on the determined energy usage estimates to meet a target energy value that is averaged for the thermal average period. The method includes adjusting, for each of the plurality of measurement periods, the power gated clock rate towards the target clock rate, wherein the adjusting causes the packet processing block to process the ingress packets at the adjusted power gated clock rate.Type: ApplicationFiled: July 31, 2020Publication date: February 3, 2022Inventors: Surendra ANUBOLU, Sachin Prabhakarrao Kadu, Laxminarasimha Rao Kesiraju, Mohan V. Kalkunte