Abstract: A wearable computing device includes a PPG sensor that includes an emitter configured to output a light signal that is modulated with a carrier signal to generate a modulated light signal. The PPG sensor further includes one or more detectors configured to receive a first reflected light signal that is a reference signal of the modulated light signal without PPG data in the carrier signal and a second reflected light signal that is a reference signal of the modulated light signal with PPG data in the carrier signal. The wearable computing device further includes a control circuit configured to synchronously demodulate the first and second instances of the modulated light signal to obtain a first demodulated signal and a second demodulated signal, respectively. The control circuit is further configured to generate data indicative of one or more aggressors affecting the PPG data based on the first and second demodulated signals.

Abstract: A wearable device includes a MEMS resonator. The MEMS resonator is configured to generate an output signal that is indicative of a temperature of a portion of the wearable device that contacts a user's skin when the wearable device is worn by the user. The wearable device includes control circuitry communicatively coupled to the MEMS resonator. The control circuitry is configured to demodulate the output signal and a local oscillator signal indicative of a setpoint temperature for the portion of the wearable device. The control circuitry is configured to determine a phase difference between a phase of the demodulated output signal and a phase of the demodulated local oscillator signal. The control circuitry is further configured to determine a temperature of the user's has changed based on the phase difference.

Abstract: Techniques for synchronizing superframes across apparatuses are disclosed. An apparatus for communication with a plurality of devices is set to a premise communication mode. While in the premise communication mode, the apparatus outputs a first superframe configured in a premise communication superframe mode allocating each slot of a plurality of slots for wireless communication to a first protocol at a first frequency band or a different second protocol. The apparatus transitions from the premise communication mode to a community communication mode. While in the community communication mode, the apparatus outputs a second superframe configured in a community communication superframe mode allocating at least one slot for wireless communication to the first protocol or the second protocol at the first frequency band, and at least one slot for wireless communication to a community beacon including data relating to a unique key recognizable by a remote apparatus.

Abstract: A system includes a sensor device, a hub device, and a keypad device. The keypad device is configured to operate in a keypad mode and a wireless repeater mode. In the wireless repeater mode, the keypad device is in communication with the hub device and in direct communication with the sensor device such that the keypad device, in the wireless repeater mode, acts as a wireless repeater between the hub device and the sensor device.

Abstract: A known signal is sent to a resistor of a mobile computing device, wherein the resistor directly contacts a surface. A signal is from the resistor, wherein the signal comprises the known signal and a degree of thermal noise from the resistor, and wherein the degree of thermal noise is associated with a temperature of the surface. The thermal noise is extracted from the signal from the resistor. The temperature of the surface is determined based on the thermal noise extracted from the signal from the resistor.

Abstract: A register management system is coupled to a register. The register management system receives an address and functional data for a write operation to be performed on the register. The functional data includes write bits and mask bits associated with the write bits. One or more mask bits having a first logic state indicate that associated one or more write bits are to be written to the register, respectively. Based on the address, the register management system selects a first half of the register or a second half of the register to perform the write operation. Further, the register management system writes the one or more write bits associated with the one or more mask bits having the first logic state to one or more storage elements of the first half of the register or the second half of the register, respectively.

Abstract: A system includes a sensor device, a repeater, and a control panel. The sensor device is in two-way communication with the repeater, and the repeater is in two-way communication with the control panel. The repeater includes a repeater module storing child table data and routing table data. The child table data stored by the repeater module, at the repeater, includes a sensor device address, sensor device descriptor, and/or sensor device status. The routing table data stored by the repeater module, at the repeater, includes channel operational information, such as a network ID, a first repeater operating channel of the repeater, a second repeater operating channel for the repeater different than the first repeater operating channel, a first information channel, and/or a second information channel different than the first information channel.

Abstract: A system includes a sensor device, a hub device, and a keypad device. The keypad device is configured to operate in a keypad mode and a wireless repeater mode. In the wireless repeater mode, the keypad device is in communication with the hub device and in direct communication with the sensor device such that the keypad device, in the wireless repeater mode, acts as a wireless repeater between the hub device and the sensor device.

Abstract: A register management system is coupled to a register. The register management system receives an address and functional data for a write operation to be performed on the register. The functional data includes write bits and mask bits associated with the write bits. One or more mask bits having a first logic state indicate that associated one or more write bits are to be written to the register, respectively. Based on the address, the register management system selects a first half of the register or a second half of the register to perform the write operation. Further, the register management system writes the one or more write bits associated with the one or more mask bits having the first logic state to one or more storage elements of the first half of the register or the second half of the register, respectively.

Abstract: A multi-clock domain system includes a synchronizer circuit. The synchronizer circuit includes a sequential logic circuit and a synchronizing stage. The sequential logic circuit receives a functional signal that is generated based on a first clock signal that is further associated with a first clock domain, a second clock signal that is associated with a second clock domain, and a reference signal. Based on the first and second clock signals and the reference signal, the synchronizer circuit outputs a logic signal. When the functional signal is activated, the logic signal is activated and remains activated for a predetermined time duration after the functional signal is deactivated. The synchronizing stage receives the second clock signal and further receives the logic signal from the sequential logic circuit, and outputs a synchronized functional signal.

Abstract: A system includes a sensor device, a hub device, and a keypad device. The hub device is in communication with the sensor device using time divisional multiple access (TDMA) The keypad device is in communication with the hub device. The keypad device is configured to operate in: a keypad mode and a wireless repeater mode. In the keypad mode, the keypad device is in communication with the hub device but not in direct communication with the sensor device. In the wireless repeater mode, the keypad device is in communication with the hub device and in direct communication with the sensor device using TDMA such that the keypad device, in the wireless repeater mode, acts as a wireless repeater between the hub device and the sensor device.

Abstract: A system includes a sensor device, a hub device, and a keypad device. The hub device is in communication with the sensor device using time divisional multiple access (TDMA) The keypad device is in communication with the hub device. The keypad device is configured to operate in: a keypad mode and a wireless repeater mode. In the keypad mode, the keypad device is in communication with the hub device but not in direct communication with the sensor device. In the wireless repeater mode, the keypad device is in communication with the hub device and in direct communication with the sensor device using TDMA such that the keypad device, in the wireless repeater mode, acts as a wireless repeater between the hub device and the sensor device.

Abstract: Systems and methods for reducing interference in a TDMA based wireless network are provided. Such systems and methods can include a wireless access point forming a wireless network, the wireless access point selecting a first information channel, a second information channel, and a plurality of operating channel sequences from a plurality of wireless network channels used by the wireless network, the wireless access point assigning a first operating channel sequence of the plurality of operating channel sequences to the wireless access point and a second operating channel sequence of the plurality of operating channel sequences to a wireless repeater, the wireless access point hopping between each one of the first operating channel sequence in different ones of superframes used by the wireless network, and the wireless repeater hopping between each one of the second operating channel sequence in the different ones of the superframes.

Abstract: Systems and methods for reducing interference in a TDMA based wireless network are provided. Such systems and methods can include a wireless access point forming a wireless network, the wireless access point selecting a first information channel, a second information channel, and a plurality of operating channel sequences from a plurality of wireless network channels used by the wireless network, the wireless access point assigning a first operating channel sequence of the plurality of operating channel sequences to the wireless access point and a second operating channel sequence of the plurality of operating channel sequences to a wireless repeater, the wireless access point hopping between each one of the first operating channel sequence in different ones of superframes used by the wireless network, and the wireless repeater hopping between each one of the second operating channel sequence in the different ones of the superframes.

Abstract: For a baseband digital front-end (BDFE) processor that communicates with one or more radio-frequency integrated circuit (RFIC) chips over two or more JESD-compliant links in a multi-antenna base station, the BDFE has JESD transmitters (TXs) and receivers (RXs) that transmit and receive data to and from the RFIC chips and a time-based generator (TBGEN) that generates sync and idle signals that ensure that the processing of the different JESD TXs and RXs are aligned in time for data associated with a single logical group of antennas. The TBGEN has hardware-based alignment circuitry that generates the sync and idle signals, thereby avoiding the latency and unpredictability inherent with software-based solutions.

Abstract: A transmission node includes a digital front-end device that provides functional clocks for JESD204B based data transmission. The front-end device includes a PLL for generating a phase locked clock based on a device clock of the front-end device, a clock dividing unit for generating the functional clocks by dividing the phase locked clock, a clock gating unit connected between the PLL and the clock dividing unit, and a system reference signal sampling unit for timing radio frame boundaries. The clock gating unit gates the phase locked clock to align the functional clocks with the device clock within a predetermined number of cycles of the phase locked clock, upon locking of the PLL or receipt of a system resynchronization request. The system reference signal sampling unit samples the system reference signal with zero-cycle latency between device clock and phase locked clock.

Abstract: An integrated circuit (IC) in an unresponsive radio equipment (RE) node includes a common public radio interface (CPRI) controller, a processor, and a system reset controller that includes an L1 (Layer 1) reset controller. The CPRI controller generates a reset request signal based on a CPRI reset request received from an RE controller (REC). The L1 reset controller generates a traffic stop signal based on the reset request signal. The CPRI controller generates a traffic idle signal based on the traffic stop signal. The L1 reset controller receives the traffic idle signal before a predetermined time period and generates a system reset signal for resetting the processor, thereby recovering the unresponsive RE node without disrupting the network topology of a communication system that includes the REC and multiple RE nodes including the unresponsive RE node connected via a CPRI link.

Abstract: A transmission node includes a digital front-end device that provides functional clocks for JESD204B based data transmission. The front-end device includes a PLL for generating a phase locked clock based on a device clock of the front-end device, a clock dividing unit for generating the functional clocks by dividing the phase locked clock, a clock gating unit connected between the PLL and the clock dividing unit, and a system reference signal sampling unit for timing radio frame boundaries. The clock gating unit gates the phase locked clock to align the functional clocks with the device clock within a predetermined number of cycles of the phase locked clock, upon locking of the PLL or receipt of a system resynchronization request. The system reference signal sampling unit samples the system reference signal with zero-cycle latency between device clock and phase locked clock.

Abstract: The present invention provides cost efficient two way authentication method in which the authentication module can be provided as a Plug and Play (PnP) architecture enabling dual layer security with reduced cost where the actions are initiated by a server and user input is received through an audio session for added security. The second level authentication can be carried out with mobile as client device making it cost efficient. The invention can be hosted as an independent service or can be integrated with existing authentication mechanisms, making it elegant for usage.

Abstract: The present invention provides cost efficient two way authentication method in which the authentication module can be provided as a Plug and Play (PnP) architecture enabling dual layer security with reduced cost where the actions are initiated by a server and user input is received through an audio session for added security. The second level authentication can be carried out with mobile as client device making it cost efficient. The invention can be hosted as an independent service or can be integrated with existing authentication mechanisms, making it elegant for usage.