Patents by Inventor Sachin Ramesh Gugwad

Sachin Ramesh Gugwad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11979262
    Abstract: Various embodiments provide for identifying and training a floating tap for decision feedback equalization. For some embodiments, the identification and training of the floating tap described herein can be part of a circuit for receiver block of a system, such as a memory system.
    Type: Grant
    Filed: January 6, 2022
    Date of Patent: May 7, 2024
    Assignee: Cadence Design Systems, Inc.
    Inventors: Hari Anand Ravi, Sachin Ramesh Gugwad
  • Patent number: 11580048
    Abstract: Various aspects of the subject technology relate to systems, methods, and machine-readable media for DDR reference voltage training. The method includes receiving a data stream, the data stream including pulses generated from a reference voltage in relation to a voltage input logic low and a voltage input logic high of an input stream. The method also includes receiving a clock signal, the clock signal including an in-phase signal and a quadrature-phase signal, the in-phase signal orthogonal to the quadrature-phase signal. The method also includes utilizing the in-phase signal and the quadrature-phase signal of the clock signal in relation to the data stream to obtain a stream of in-phase samples and a stream of quadrature-phase samples. The method also includes adjusting the reference voltage based on a relationship of the stream of in-phase samples to the stream of quadrature-phase samples.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: February 14, 2023
    Inventors: Thomas E. Wilson, Scott Huss, Hari Anand Ravi, Sachin Ramesh Gugwad, Balbeer Singh Rathor
  • Patent number: 11483185
    Abstract: Disclosed is an improved approach for a training approach to implement DFE for an electronic circuit. The inventive concept is particularity suitable to address, for example, circuits that implement high speed parallel data transmission protocols, such as GDDR6, that are used for graphics applications. The training scheme uses minimal hardware when compared to existing schemes by reusing calibration receiver in auto zeroing receiver as error receiver. Further it works for closed eyes by running the algorithm multiple times with gradual increase in complexity of training pattern, where DFE coefficients from previous iteration is used for the current iteration, thereby gradually opening the eye.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: October 25, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Sachin Ramesh Gugwad, Hari Anand Ravi, Aaron Willey, Thomas E. Wilson
  • Patent number: 11323296
    Abstract: The embodiments described herein provide for a method and system for training an optimal decision feedback equalization (DFE) coefficient for use in GDDR and DDR applications. The method includes determining a first expected bit pattern using a reference voltage. The method further includes determining a transition voltage value of the first expected bit pattern. The method further includes receiving a second expected bit pattern having a same first bit as the first expected bit pattern. The method further includes determining a transition voltage value of the second expected bit pattern using the reference voltage. The method further includes calculating an optimal reference voltage value by averaging the transition voltage values of the first expected bit pattern and the second-expected bit pattern and storing the optimal reference voltage value in a register corresponding to a logic value of the same first bit.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: May 3, 2022
    Inventors: Sachin Ramesh Gugwad, Hari Anand Ravi, Thomas E Wilson, Vinod Kumar
  • Patent number: 10771108
    Abstract: Embodiments relate to systems, methods, and computer-readable media to enable design and creation of crosstalk cancellation circuitry for a receiver (e.g. an AC coupled DDR5 receiver). One embodiment is a receiver apparatus with crosstalk victim and aggressors lines. The cancellation circuitry involves an amplifier and buffering circuitry to provide inductive and capacitive crosstalk cancellation voltages. Some embodiments can additionally involve circuitry for autozeroing modes for AC coupled receiver lines.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: September 8, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: H Md Shuaeb Fazeel, Sachin Ramesh Gugwad
  • Patent number: 9754646
    Abstract: Embodiments relate to circuits, electronic design automation (EDA) circuit layouts, systems, methods, and computer readable media to enable logic devices operating on a core supply voltage to drive memory devices operating on a different supply voltage using low power and high data rates while avoiding voltage over-stress of thin-oxide transistors. In an embodiment, channels of a thin-oxide PMOS transistor, a thick-oxide PMOS transistor, a thick-oxide NMOS transistor, and a thin-oxide NMOS transistor are coupled in order from a memory device voltage supply rail to a low voltage supply rail. Gates of the thin-oxide PMOS transistor and the thick-oxide NMOS transistor are coupled with an output of a flying capacitor circuit that level-shifts an input signal by a difference between the memory device supply and core supply voltages, while gates of the thick-oxide PMOS transistor and the thin-oxide NMOS transistor receive the input signal via a buffer.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: September 5, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Vinod Kumar, Tara Vishin, Sachin Ramesh Gugwad, Thomas Evan Wilson