Abstract: A logic-memory cell includes a spin-orbit torque device having first, second and third terminals configured such that current between the second and third terminals is capable of changing a resistance between the first and second terminals. In the cell, a first transistor is connected between a logic connection line and the first terminal of the spin-orbit torque device and a second transistor is connected between the logic connection line and the third terminal of the spin-orbit torque device.

Abstract: A logic-memory cell includes a spin-orbit torque device having first, second and third terminals configured such that current between the second and third terminals is capable of changing a resistance between the first and second terminals. In the cell, a first transistor is connected between a logic connection line and the first terminal of the spin-orbit torque device and a second transistor is connected between the logic connection line and the third terminal of the spin-orbit torque device.

Abstract: In some examples, an electronic device comprising an input ferroelectric (FE) capacitor, an output FE capacitor, and a channel positioned beneath the input FE capacitor and positioned beneath the output FE capacitor. In some examples, the channel is configured to carry a magnetic signal from the input FE capacitor to the output FE capacitor to cause a voltage change at the output FE capacitor. In some examples, the electronic device further comprises a transistor-based drive circuit electrically connected to an output node of the output FE capacitor. In some examples, the transistor-based drive circuit is configured to deliver, based on the voltage change at the output FE capacitor, an output signal to an input node of a second device.

Abstract: In some examples, an electronic device comprising an input ferroelectric (FE) capacitor, an output FE capacitor, and a channel positioned beneath the input FE capacitor and positioned beneath the output FE capacitor. In some examples, the channel is configured to carry a magnetic signal from the input FE capacitor to the output FE capacitor to cause a voltage change at the output FE capacitor. In some examples, the electronic device further comprises a transistor-based drive circuit electrically connected to an output node of the output FE capacitor. In some examples, the transistor-based drive circuit is configured to deliver, based on the voltage change at the output FE capacitor, an output signal to an input node of a second device.

Abstract: A circuit design system includes a simulator that determines an average charging current provided by each current insertion point in a cell and an average charging current along a path in the cell between a reference pin position and a candidate pin position. A candidate pin placement tester updates the average charging current along the path by adding the average charging current of each insertion point to the average charging current along the path to produce an updated average charging current along the path and uses the updated average charging current along the path to determine a time to failure for the cell.

Abstract: A circuit design system includes a simulator that determines an average charging current provided by each current insertion point in a cell and an average charging current along a path in the cell between a reference pin position and a candidate pin position. A candidate pin placement tester updates the average charging current along the path by adding the average charging current of each insertion point to the average charging current along the path to produce an updated average charging current along the path and uses the updated average charging current along the path to determine a time to failure for the cell.