Patents by Inventor Sachin Satish Idgunji
Sachin Satish Idgunji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11669421Abstract: Unavoidable physical phenomena, such as an alpha particle strikes, can cause soft errors in integrated circuits. Materials that emit alpha particles are ubiquitous, and higher energy cosmic particles penetrate the atmosphere and also cause soft errors. Some soft errors have no consequence, but others can cause an integrated circuit to malfunction. In some applications (e.g. driverless cars), proper operation of integrated circuits is critical to human life and safety. To minimize or eliminate the likelihood of a soft error becoming a serious malfunction, detailed assessment of individual potential soft errors and subsequent processor behavior is necessary. Embodiments of the present disclosure facilitate emulating a plurality of different, specific soft errors. Resilience may be assessed over the plurality of soft errors and application code may be advantageously engineered to improve resilience.Type: GrantFiled: February 2, 2022Date of Patent: June 6, 2023Assignee: NVIDIA CorporationInventors: Jonah M. Alben, Sachin Satish Idgunji, Jue Wu
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Publication number: 20230007920Abstract: Graphics processing unit (GPU) performance and power efficiency is improved using machine learning to tune operating parameters based on performance monitor values and application information. Performance monitor values are processed using machine learning techniques to generate model parameters, which are used by a control unit within the GPU to provide real-time updates to the operating parameters. In one embodiment, a neural network processes the performance monitor values to generate operating parameters in real-time.Type: ApplicationFiled: September 15, 2022Publication date: January 12, 2023Inventors: Rouslan L. Dimitrov, Dale L. Kirkland, Emmett M. Kilgariff, Sachin Satish Idgunji, Siddharth Sharma
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Patent number: 11481950Abstract: Graphics processing unit (GPU) performance and power efficiency is improved using machine learning to tune operating parameters based on performance monitor values and application information. Performance monitor values are processed using machine learning techniques to generate model parameters, which are used by a control unit within the GPU to provide real-time updates to the operating parameters. In one embodiment, a neural network processes the performance monitor values to generate operating parameters in real-time.Type: GrantFiled: January 29, 2021Date of Patent: October 25, 2022Assignee: NVIDIA CorporationInventors: Rouslan L. Dimitrov, Dale L. Kirkland, Emmett M. Kilgariff, Sachin Satish Idgunji, Siddharth Sharma
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Publication number: 20220156169Abstract: Unavoidable physical phenomena, such as an alpha particle strikes, can cause soft errors in integrated circuits. Materials that emit alpha particles are ubiquitous, and higher energy cosmic particles penetrate the atmosphere and also cause soft errors. Some soft errors have no consequence, but others can cause an integrated circuit to malfunction. In some applications (e.g. driverless cars), proper operation of integrated circuits is critical to human life and safety. To minimize or eliminate the likelihood of a soft error becoming a serious malfunction, detailed assessment of individual potential soft errors and subsequent processor behavior is necessary. Embodiments of the present disclosure facilitate emulating a plurality of different, specific soft errors. Resilience may be assessed over the plurality of soft errors and application code may be advantageously engineered to improve resilience.Type: ApplicationFiled: February 2, 2022Publication date: May 19, 2022Inventors: Jonah M. Alben, Sachin Satish Idgunji, Jue Wu
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Patent number: 11275662Abstract: Unavoidable physical phenomena, such as an alpha particle strikes, can cause soft errors in integrated circuits. Materials that emit alpha particles are ubiquitous, and higher energy cosmic particles penetrate the atmosphere and also cause soft errors. Some soft errors have no consequence, but others can cause an integrated circuit to malfunction. In some applications (e.g. driverless cars), proper operation of integrated circuits is critical to human life and safety. To minimize or eliminate the likelihood of a soft error becoming a serious malfunction, detailed assessment of individual potential soft errors and subsequent processor behavior is necessary. Embodiments of the present disclosure facilitate emulating a plurality of different, specific soft errors. Resilience may be assessed over the plurality of soft errors and application code may be advantageously engineered to improve resilience.Type: GrantFiled: January 7, 2021Date of Patent: March 15, 2022Assignee: NVIDIA CorporationInventors: Jonah M. Alben, Sachin Satish Idgunji, Jue Wu
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Patent number: 11106261Abstract: Integrated circuits, or computer chips, typically include multiple hardware components (e.g. memory, processors, etc.) operating under a shared power (e.g. thermal) constraint that is sourced by one or more power sources for the chip. Typically, the hardware components can be individually configured to operate at certain states (e.g. to operate at a certain frequency by setting a clock speed for a clock dedicated to the hardware component). Thus, each hardware component can be configured to operate at an operating point that is determined to be optimal, usually in terms of achieving some desired goal for a specific application (e.g. frame rates for gaming, etc.). In the context of chip hardware that operates under a shared power/thermal constraint, a method, computer readable medium, and system are provided for determining the optimal operating point for the chip that takes into consideration both performance of the chip and power consumption by the chip.Type: GrantFiled: November 2, 2018Date of Patent: August 31, 2021Assignee: NVIDIA CORPORATIONInventors: Aniket Naik, Siddharth Bhargav, Bardia Zandian, Narayan Kulshrestha, Amit Pabalkar, Arvind Gopalakrishnan, Justin Tai, Sachin Satish Idgunji
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Publication number: 20210174569Abstract: Graphics processing unit (GPU) performance and power efficiency is improved using machine learning to tune operating parameters based on performance monitor values and application information. Performance monitor values are processed using machine learning techniques to generate model parameters, which are used by a control unit within the GPU to provide real-time updates to the operating parameters. In one embodiment, a neural network processes the performance monitor values to generate operating parameters in real-time.Type: ApplicationFiled: January 29, 2021Publication date: June 10, 2021Inventors: Rouslan L. Dimitrov, Dale L. Kirkland, Emmett M. Kilgariff, Sachin Satish Idgunji, Siddharth Sharma
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Publication number: 20210157699Abstract: Unavoidable physical phenomena, such as an alpha particle strikes, can cause soft errors in integrated circuits. Materials that emit alpha particles are ubiquitous, and higher energy cosmic particles penetrate the atmosphere and also cause soft errors. Some soft errors have no consequence, but others can cause an integrated circuit to malfunction. In some applications (e.g. driverless cars), proper operation of integrated circuits is critical to human life and safety. To minimize or eliminate the likelihood of a soft error becoming a serious malfunction, detailed assessment of individual potential soft errors and subsequent processor behavior is necessary. Embodiments of the present disclosure facilitate emulating a plurality of different, specific soft errors. Resilience may be assessed over the plurality of soft errors and application code may be advantageously engineered to improve resilience.Type: ApplicationFiled: January 7, 2021Publication date: May 27, 2021Inventors: Jonah M. Alben, Sachin Satish Idgunji, Jue Wu
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Patent number: 10922203Abstract: Unavoidable physical phenomena, such as an alpha particle strikes, can cause soft errors in integrated circuits. Materials that emit alpha particles are ubiquitous, and higher energy cosmic particles penetrate the atmosphere and also cause soft errors. Some soft errors have no consequence, but others can cause an integrated circuit to malfunction. In some applications (e.g. driverless cars), proper operation of integrated circuits is critical to human life and safety. To minimize or eliminate the likelihood of a soft error becoming a serious malfunction, detailed assessment of individual potential soft errors and subsequent processor behavior is necessary. Embodiments of the present disclosure facilitate emulating a plurality of different, specific soft errors. Resilience may be assessed over the plurality of soft errors and application code may be advantageously engineered to improve resilience.Type: GrantFiled: September 21, 2018Date of Patent: February 16, 2021Assignee: NVIDIA CorporationInventors: Jonah M. Alben, Sachin Satish Idgunji, Jue Wu
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Patent number: 10909738Abstract: Graphics processing unit (GPU) performance and power efficiency is improved using machine learning to tune operating parameters based on performance monitor values and application information. Performance monitor values are processed using machine learning techniques to generate model parameters, which are used by a control unit within the GPU to provide real-time updates to the operating parameters. In one embodiment, a neural network processes the performance monitor values to generate operating parameters in real-time.Type: GrantFiled: January 5, 2018Date of Patent: February 2, 2021Assignee: NVIDIA CorporationInventors: Rouslan L. Dimitrov, Dale L. Kirkland, Emmett M. Kilgariff, Sachin Satish Idgunji, Siddharth Sharma
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Publication number: 20200142466Abstract: Integrated circuits, or computer chips, typically include multiple hardware components (e.g. memory, processors, etc.) operating under a shared power (e.g. thermal) constraint that is sourced by one or more power sources for the chip. Typically, the hardware components can be individually configured to operate at certain states (e.g. to operate at a certain frequency by setting a clock speed for a clock dedicated to the hardware component). Thus, each hardware component can be configured to operate at an operating point that is determined to be optimal, usually in terms of achieving some desired goal for a specific application (e.g. frame rates for gaming, etc.). In the context of chip hardware that operates under a shared power/thermal constraint, a method, computer readable medium, and system are provided for determining the optimal operating point for the chip that takes into consideration both performance of the chip and power consumption by the chip.Type: ApplicationFiled: November 2, 2018Publication date: May 7, 2020Inventors: Aniket Naik, Siddharth Bhargav, Bardia Zandian, Narayan Kulshrestha, Amit Pabalkar, Arvind Gopalakrishnan, Justin Tai, Sachin Satish Idgunji
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Publication number: 20190213775Abstract: Graphics processing unit (GPU) performance and power efficiency is improved using machine learning to tune operating parameters based on performance monitor values and application information. Performance monitor values are processed using machine learning techniques to generate model parameters, which are used by a control unit within the GPU to provide real-time updates to the operating parameters. In one embodiment, a neural network processes the performance monitor values to generate operating parameters in real-time.Type: ApplicationFiled: January 5, 2018Publication date: July 11, 2019Inventors: Rouslan L. Dimitrov, Dale L. Kirkland, Emmett M. Kilgariff, Sachin Satish Idgunji, Siddharth Sharma
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Patent number: 9269418Abstract: An apparatus comprises a dynamic random-access memory (DRAM) for storing data. Refresh control circuitry is provided to control the DRAM to periodically perform a refresh cycle for refreshing the data stored in each memory location of the DRAM. A refresh address sequence generator generates a refresh address sequence of addresses identifying the order in which memory locations of the DRAM are refreshed during the refresh cycle. To deter differential power analysis attacks on secure data stored in the DRAM, the refresh address sequence is generated with the addresses of at least a portion of the memory locations in a random order which varies from refresh cycle to refresh cycle.Type: GrantFiled: February 6, 2012Date of Patent: February 23, 2016Assignee: ARM LimitedInventors: Donald Felton, Emre Özer, Sachin Satish Idgunji
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Patent number: 9141338Abstract: A storage circuit 2 in the form of a master slave latch includes a slave stage 6 serving as a bit storage circuit. The slave stage 6 includes an inverter chain which when operating in a normal mode includes an even number of inverters 10, 12 and when operating in an random number generation mode includes an odd number of inverters 10, 12, 14 and so functions as a free running ring oscillator. When a switch is made back from the random number generation mode to the normal mode, then the oscillation ceases and a stable pseudo random bit value is output from the bit value storage circuit 6.Type: GrantFiled: November 16, 2012Date of Patent: September 22, 2015Assignee: ARM LimitedInventors: Sachin Satish Idgunji, Vikas Chandra
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Patent number: 9110643Abstract: An integrated circuit is provided with operational mode header transistors which connect a virtual power rail to a VDD power supply. A controller circuit, responsive to a sensed voltage signal from a voltage sensor which reads the virtual rail voltage VVDD, generates a control signal which controls the operational mode transistors. The control signal is derived from an interface voltage power supply that provides higher voltage VDD IO than the VDD power supply and thus able to overdrive the operational mode transistors via either a gate bias voltage or a bulk bias voltage. The amount of leakage through the operational mode transistors is controlled in a closed loop feedback arrangement so as to maintain a predetermined target value or range for the virtual rail voltage. The operational mode transistor may also be controlled to support dynamic voltage and frequency scaling.Type: GrantFiled: June 11, 2012Date of Patent: August 18, 2015Assignee: ARM LimitedInventors: Sachin Satish Idgunji, Bal S Sandhu
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Patent number: 8830783Abstract: A semiconductor memory storage device is disclosed. The memory comprises a plurality of storage cells for storing data each storage cell comprising an access control device for providing the storage cell with access to or isolation from a data access port in response to an access control signal, access control circuitry for transmitting the access control signal along an access control line to control a plurality of the access control devices connected to the access control line.Type: GrantFiled: January 3, 2011Date of Patent: September 9, 2014Assignee: ARM LimitedInventors: Sachin Satish Idgunji, Hemangi Umakant Gajjewar, Vincent Phillipe Schuppe, Yew Keong Chong, Hsin-Yu Chen
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Patent number: 8826097Abstract: A data processing apparatus is provided which comprises a processor unit configured to perform data processing operations in response to a sequence of instructions and a storage unit configured to store data values for access by the processor unit when performing its data processing operations. Redundant error control data is stored in association with the data values, the redundant error control data enabling identification of an error in the data values. The data processing apparatus also comprises a data scrubbing unit configured to perform a data scrubbing process on at least a subset of the data values, the data scrubbing process comprising determining with reference to the redundant error control data if an error is present in that subset of data values and, where possible, correcting that error with reference to the redundant error control data.Type: GrantFiled: March 30, 2011Date of Patent: September 2, 2014Assignee: ARM LimitedInventors: Emre Özer, Sachin Satish Idgunji
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Publication number: 20140143291Abstract: A storage circuit 2 in the form of a master slave latch includes a slave stage 6 serving as a bit storage circuit. The slave stage 6 includes an inverter chain which when operating in a normal mode includes an even number of inverters 10, 12 and when operating in an random number generation mode includes an odd number of inverters 10, 12, 14 and so functions as a free running ring oscillator. When a switch is made back from the random number generation mode to the normal mode, then the oscillation ceases and a stable pseudo random bit value is output from the bit value storage circuit 6.Type: ApplicationFiled: November 16, 2012Publication date: May 22, 2014Applicant: ARM LIMITEDInventors: Sachin Satish IDGUNJI, Vikas CHANDRA
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Patent number: 8717078Abstract: A latching device includes input and output latching elements to receive and output data values wherein the input and output elements are configured to receive a first and second clocks, respectively. The clocks have the same frequency but are inverted. The elements are transparent and transmit data between an input and an output in response to the first value of a received clock and are opaque and hold the data value in response to a second value of the received clock, such that in response to the first and second clocks the input data value is clocked through the input and output elements to the output. The device includes a device for selecting an operational data value or a diagnostic data value for input to the input element in response to a value of a diagnostic enable signal indicating a functional mode or a diagnostic mode.Type: GrantFiled: June 13, 2012Date of Patent: May 6, 2014Assignee: ARM LimitedInventors: Sachin Satish Idgunji, Robert Campbell Aitken, Imran Iqbal
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Patent number: 8639960Abstract: A data processing apparatus is provided comprising data processing circuitry configured to perform data processing operations. A plurality of state retention circuits forms part of the data processing circuitry and these circuits are configured to hold respective state values at respective nodes of the data processing circuitry it enters a low power mode. One or more scan paths connect the plurality of state retention circuits together in series, such that the state values may be scanned into and out of the respective nodes. A plurality of parity information generation elements are coupled to the scan path(s) and configured to generate parity information indicative of the respective state values held at those respective nodes by the state retention circuits.Type: GrantFiled: May 27, 2011Date of Patent: January 28, 2014Assignee: ARM LimitedInventors: David Walter Flynn, Sachin Satish Idgunji