Abstract: A charge domain filter circuit includes a first signal output portion, at least one second signal output, portion, a third signal output portion, and an adder portion. The first signal output portion outputs a first signal that is sampled at a specified time interval. Each second signal, output portion outputs a second signal that is sampled after a specified delay after the first signal is sampled. Where a plurality of the second signal output portions is included, the second signals are sampled in succession. The third signal output portion outputs a third signal that is sampled after a specified delay after the last second signal is sampled. The adder portion adds the first, second, and third signals together and outputs the result. The capacitance ratio of the sampling capacitors in the first signal output portion and the second signal output portion is one of continuously or discretely varied.

Abstract: There is provided a signal processing apparatus including a variable capacitor and a switching portion for switching the circuit mode between a sampling mode, in which the variable capacitor samples an input signal, a holding mode, in which a charge gained by sampling the input signal is held in the variable capacitor, and an output mode for outputting the charge stored in the variable capacitor, wherein the variable capacitor is provided with an input terminal through which the input signal is inputted in the sampling mode, a control terminal to which a first control signal which decreases the capacitance of the variable capacitor to a value below the capacitance in the sampling mode is inputted in the output mode, and a second control signal having a predetermined reference voltage is inputted in the holding mode, where an insulating layer is provided between the control terminal and the input terminal.

Abstract: A filter circuit includes a voltage-current conversion portion that converts a voltage signal input to an input terminal to a current signal, a first capacitor unit formed by a plurality of capacitors, and in which a current signal output from the voltage-current conversion portion is sequentially input to the capacitors, the unit adding and outputting electric charges of a group of capacitors to which the current signal is input, a second capacitor unit formed by a plurality of capacitors, and in which a current signal output from the first capacitor unit is sequentially input to the capacitors, the unit adding and outputting electric charges of a group of capacitors to which the current signal is input, and a plurality of connection nodes that respectively connect a given capacitor in the first capacitor unit and a capacitor in the second capacitor unit.

Abstract: A switched capacitor circuit includes a capacitor that performs sampling, a first switch that is provided between the capacitor and an input terminal, and a second switch that is provided between the capacitor and an output terminal. The first switch and the second switch receive an input of a clock signal and turn on and off. The capacitor is a variable capacitance element in which the value of the capacitance changes in synchronization with the clock signal.

Abstract: A filter circuit according to the present invention includes a voltage-current conversion unit that converts a voltage signal input to an input end to a current signal, a capacitor group that is made up of a plurality of capacitors, where the current signal output from the voltage-current conversion unit is sequentially input to each capacitor at every cycle, a first switch that connects a set of capacitors to which the current signal is input with each other and adds charges accumulated in the set of capacitors together, and a second switch that connects at least one capacitor of the set of capacitors to an output end after charges are added by the first switch.

Abstract: A multiband OFDM_UWB transmitting and receiving apparatus is provided in Low-IF configuration to solve problems attributed to a direct-conversion transmitting and receiving apparatus. A Low-IF receiver performs sorting by rotating a sub-carrier after FFT to eliminate the need for frequency conversion using a second local signal and uses the same AD conversion clock as that for a direct conversion receiver. An FFT-free preamble can be detected by using a sequence resulting from previously multiplying an original preamble pattern and an IF frequency together.

Abstract: There is provided a filter circuit that includes: a flying capacitor which maintains polarity when switching from an input terminal to an output terminal, and the polarity of which is reversed when switching from the output terminal to the input terminal; a first capacitor that is provided in parallel to the flying capacitor, at the input terminal of the flying capacitor; and a second capacitor that is provided in parallel to the flying capacitor, at the output terminal of the flying capacitor. The flying capacitor includes a variable capacity element such that capacity becomes smaller when switching from the input terminal to the output terminal and capacity becomes larger when switching from the output terminal to the input terminal.

Abstract: There is provided a filter circuit that includes: a flying capacitor which maintains polarity when switching from an input terminal to an output terminal, and the polarity of which is reversed when switching from the output terminal to the input terminal; a first capacitor that is provided in parallel with the flying capacitor, at the input terminal of the flying capacitor; and a second capacitor that is provided in parallel with the flying capacitor, at the output terminal of the flying capacitor. The flying capacitor is switched from the input terminal to the output terminal with a delay of a predetermined time after the switching from the output terminal to the input terminal, and the flying capacitor is switched from the output terminal to the input terminal with a delay of a predetermined time after the switching from the input terminal to the output terminal.

Abstract: There is provided a filter circuit that includes a flying capacitor and a capacitor that is provided in parallel with the flying capacitor, between an input terminal and an output terminal of the flying capacitor. As the capacitor that has a predetermined capacity is provided between the input terminal and the output terminal of the flying capacitor, it is possible to provide steep attenuation characteristics in the filter circuit provided with the flying capacitor.

Abstract: A charge domain filter device includes a SINC filter with a frequency characteristic expressed by a SINC function, and a bandpass filter connected to an output end of the SINC filter and having a frequency characteristic with a particular center frequency.

Abstract: A reference frequency of 4224 MHz is divided into ½ to obtain a sampling frequency of 2112 MHz, and further the frequency division into ½ is sequentially performed and the values of three bits outputted by the ½, ¼ and ? frequency division are decoded in response to frequency selection. From one set of nonlinear 2-bit DA converters which output amplitudes {?1.7, ?0.7, 0.7, 1.7} using these decoded values as input, complex amplitudes corresponding to eight phases in a complex plane are outputted, so that complex sine waves are generated. Using these complex sine waves, the frequency switching is performed. Center frequencies of respective bands can be obtained without a phase error or an amplitude error.

Abstract: A multiband OFDM_UWB transmitting and receiving apparatus is provided in Low-IF configuration to solve problems attributed to a direct-conversion transmitting and receiving apparatus. A Low-IF receiver performs sorting by rotating a sub-carrier after FFT to eliminate the need for frequency conversion using a second local signal and uses the same AD conversion clock as that for a direct conversion receiver. An FFT-free preamble can be detected by using a sequence resulting from previously multiplying an original preamble pattern and an IF frequency together.

Abstract: A solid-state image sensing device includes a pixel unit that includes pixels, each of pixels outputting the pixel signal to a signal line connected thereto; and an amplifying unit that includes amplifiers connected to the corresponding signal lines. The amplifier includes a first variable capacitance element, a second variable capacitance element, and an input unit that selectively inputs the pixel signal to the first variable capacitance element and the second variable capacitance element. The amplifier sets the capacitances of the first variable capacitance element and the second variable capacitance element to a first value when the pixel signal is input to the first variable capacitance element and the second variable capacitance element. And the amplifier changes the capacitances of the first variable capacitance element and the second variable capacitance element to a second value that is smaller than the first value, thereby amplifying the pixel signal.

Abstract: An amplifier is provided which includes: a first variable capacitance device of which capacitance is variable, a second variable capacitance device of which capacitance is variable, electrically connected to the first variable capacitance device, and of an inverse conductivity type from the first variable capacitance device, and a first input unit for selectively inputting a bias voltage and a voltage signal to the first variable capacitance device and the second variable capacitance device, wherein, in the event that the bias voltage and the voltage signal are input to the first variable capacitance device and the second variable capacitance device, the capacitance of the first variable capacitance device and the second variable capacitance device is taken as a first value, and wherein the voltage signal is amplified with the capacitance of the first variable capacitance device and the second variable capacitance device as a second value smaller than the first value.

Abstract: For the purpose of efficient transmission based on the UWB system, first and second baseband waveforms are generated at a cycle equivalent to an integral multiple of a carrier to have a specified phase difference from each other. The first baseband waveform is multiplied by the carrier and a first transmission data sequence to acquire a first transmission waveform. The second baseband waveform is multiplied by a phase shifted carrier and a second transmission data sequence to acquire a second transmission waveform. The first transmission waveform is mixed with the second transmission waveform to acquire a transmission signal. The transmission signal is transmitted as a ?/2 shift BPSK signal to transmit a UWB signal. Selecting the baseband waveforms and the carrier makes it possible to configure the transmission band and easily provide division multiplexing transmission.

Abstract: (Problem) To provide a charge sampling filter circuit and a charge sampling method. (Means for Resolution) A charge sampling filter circuit includes a first capacitor that samples an input signal, and in which at least a portion of electric charge stored in the first capacitor by sampling is output to a second capacitor that is connectable with the first capacitor. The charge sampling filter circuit is characterized by including a switching portion that switches a circuit mode including a sampling mode that causes the first capacitor to sample the input signal, and an output mode that causes the first capacitor and the second capacitor to be connected. A capacitance value of the first capacitor in the output mode is set to be lower than the capacitance value in the sampling mode.

Abstract: A switched capacitor circuit includes a capacitor that performs sampling, a first switch that is provided between the capacitor and an input terminal, and a second switch that is provided between the capacitor and an output terminal. The first switch and the second switch receive an input of a clock signal and turn on and off. The capacitor is a variable capacitance element in which the value of the capacitance changes in synchronization with the clock signal.

Abstract: A charge domain filter circuit includes a first signal output portion, a second signal output portion, and an adder portion. The first signal output portion outputs a first signal that is sampled at a specified time interval. The second signal output portion outputs a second signal that is sampled at the same time interval as the first signal and at a different time. The adder portion adds the first signal and the second signal together and outputs the result. The second signal output portion is capable of selecting the time to sample the second signal from among a plurality of times.

Abstract: A charge domain filter circuit includes a first signal output portion, at least one second signal output, portion, a third signal output portion, and an adder portion. The first signal output portion outputs a first signal that is sampled at a specified time interval. Each second signal, output portion outputs a second signal that is sampled after a specified delay after the first signal is sampled. Where a plurality of the second signal output portions is included, the second signals are sampled in succession. The third signal output portion outputs a third signal that is sampled after a specified delay after the last second signal is sampled. The adder portion adds the first, second, and third signals together and outputs the result. The capacitance ratio of the sampling capacitors in the first signal output portion and the second signal output portion is one of continuously or discretely varied.

Abstract: There is provided a charge domain filter device including a plurality of transconductors each of which converts an input voltage to a current and outputs the current and a filter unit that filters output signals from said plurality of transconductors by repeatedly charging and discharging a plurality of capacitors, wherein an impulse response of the charge domain filter device is obtained through convolution of a first impulse corresponding to a charge time length over which said capacitors are charged and a second impulse corresponding to each of said plurality of transconductors.