Patents by Inventor Sachio Ogawa

Sachio Ogawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12046301
    Abstract: A semiconductor integrated circuit includes a buffer which outputs a memory control signal to a terminal coupled to a memory device, a power supply control circuit which controls a supply of a power supply voltage from a power supply line to the buffer based on a power control signal, a pull-up control circuit configured to control a pull-up of the terminal based on a pull-up control signal, and a control signal generating circuit. The control signal generating circuit generates, during an output period, the power control signal to supply the power supply voltage to the buffer, and the pull-up control signal to stop the pull-up of the terminal, and generates, during an idle period, the power control signal to stop the supply of the power supply voltage to the buffer, and the pull-up control signal to perform the pull-up of the terminal.
    Type: Grant
    Filed: September 15, 2023
    Date of Patent: July 23, 2024
    Assignee: Socionext Inc.
    Inventors: Masanori Okinoi, Sachio Ogawa, Ryo Azumai, Kiichi Hamasaki
  • Publication number: 20240021253
    Abstract: A semiconductor integrated circuit includes a buffer which outputs a memory control signal to a terminal coupled to a memory device, a power supply control circuit which controls a supply of a power supply voltage from a power supply line to the buffer based on a power control signal, a pull-up control circuit configured to control a pull-up of the terminal based on a pull-up control signal, and a control signal generating circuit. The control signal generating circuit generates, during an output period, the power control signal to supply the power supply voltage to the buffer, and the pull-up control signal to stop the pull-up of the terminal, and generates, during an idle period, the power control signal to stop the supply of the power supply voltage to the buffer, and the pull-up control signal to perform the pull-up of the terminal.
    Type: Application
    Filed: September 15, 2023
    Publication date: January 18, 2024
    Inventors: Masanori OKINOI, Sachio OGAWA, Ryo AZUMAI, Kiichi HAMASAKI
  • Patent number: 11798635
    Abstract: A semiconductor integrated circuit includes a buffer which outputs a memory control signal to a terminal coupled to a memory device, a power supply control circuit which controls a supply of a power supply voltage from a power supply line to the buffer based on a power control signal, a pull-up control circuit configured to control a pull-up of the terminal based on a pull-up control signal, and a control signal generating circuit. The control signal generating circuit generates, during an output period, the power control signal to supply the power supply voltage to the buffer, and the pull-up control signal to stop the pull-up of the terminal, and generates, during an idle period, the power control signal to stop the supply of the power supply voltage to the buffer, and the pull-up control signal to perform the pull-up of the terminal.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: October 24, 2023
    Assignee: Socionext Inc.
    Inventors: Masanori Okinoi, Sachio Ogawa, Ryo Azumai, Kiichi Hamasaki
  • Publication number: 20220093189
    Abstract: A semiconductor integrated circuit includes a buffer which outputs a memory control signal to a terminal coupled to a memory device, a power supply control circuit which controls a supply of a power supply voltage from a power supply line to the buffer based on a power control signal, a pull-up control circuit configured to control a pull-up of the terminal based on a pull-up control signal, and a control signal generating circuit. The control signal generating circuit generates, during an output period, the power control signal to supply the power supply voltage to the buffer, and the pull-up control signal to stop the pull-up of the terminal, and generates, during an idle period, the power control signal to stop the supply of the power supply voltage to the buffer, and the pull-up control signal to perform the pull-up of the terminal.
    Type: Application
    Filed: December 2, 2021
    Publication date: March 24, 2022
    Inventors: Masanori Okinoi, Sachio Ogawa, Ryo Azumai, Kiichi Hamasaki
  • Publication number: 20050192787
    Abstract: A simulation apparatus of a semiconductor integrated circuit, capable of measuring power consumption in a higher abstract degree than an RT level and in a high speed, is realized, so that a low power consumption designing operation can be carried out by employing a simulation result. While a cycle base model of a designing subject circuit is arranged by a state control module model, a calculation module model, and a memory model, in the calculation module model, an algorithm description is made; a detailed structure such as a pipeline of hardware is shortcircuited to a calculation to be processed in a unit clock; and a timing shift is absorbed in a wait state of the state control module model, so that a high-speed simulation can be realized. Since such information as an area and a wiring capacitance is added to an activating ratio measurement of a simulation model, power consumption can be measured.
    Type: Application
    Filed: February 25, 2005
    Publication date: September 1, 2005
    Inventors: Yuji Kuwahara, Hiroki Shinde, Sachio Ogawa
  • Patent number: 6909303
    Abstract: There are provided a plurality of semiconductor chips 102 and 103 having input/output cells 106 and 107 connected to an external terminal 108 of a multichip module 101 respectively, and test circuits 104 and 105 for the multichip module which serve to optionally set the states of the input/output cells.
    Type: Grant
    Filed: July 18, 2003
    Date of Patent: June 21, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Sachio Ogawa
  • Publication number: 20040041580
    Abstract: There are provided a plurality of semiconductor chips 102 and 103 having input/output cells 106 and 107 connected to an external terminal 108 of a multichip module 101 respectively, and test circuits 104 and 105 for the multichip module which serve to optionally set the states of the input/output cells.
    Type: Application
    Filed: July 18, 2003
    Publication date: March 4, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventor: Sachio Ogawa
  • Patent number: 5773743
    Abstract: An effect control method, an effect control device with the following configuration is provided on a karaoke system, which is one of audio regenerator or synthesizer systems.
    Type: Grant
    Filed: May 24, 1995
    Date of Patent: June 30, 1998
    Assignee: Sega Enterprises, Ltd.
    Inventors: Sachio Ogawa, Atsushi Kitahara, Shigenori Yokoe