Abstract: A gate driving circuit includes circuits each provided in such a manner as to, as a scanning signal, select a single clock pulse of a clock signal and output the clock pulse. The circuits each include: a transistor for outputting a scanning signal; a transistor for controlling an electric potential of a gate of the transistor so that the electric potential of the gate is at a low level; a transistor for, while the transistor is not outputting the scanning signal, controlling an electric potential of a gate of the transistor so that the electric potential of the gate is at a high level; and a transistor for, while the transistor is not in operation during a period during which an operation of the selection circuit is paused, controlling the electric potential of the gate of the transistor so that the electric potential becomes high.

Abstract: Provided is a technique of suppressing display defects such as flicker, without limiting the arrangement of data lines, in a liquid crystal display device having a display area in a non-rectangular shape. A liquid crystal display device includes an active matrix substrate 10, a counter substrate, and a liquid crystal layer. The active matrix substrate 10 includes a plurality of gate lines 11, and a plurality of data lines 12. In each of pixels defined by the gate lines 11 and the data lines 12, a pixel electrode 14 is arranged, and in a display area R, common electrodes 15 are provided. Outside the display area R, capacitance-generating parts C that generate capacitances between some gate lines 11 among the plurality of gate lines 11 and the common electrode are provided. The some gate lines 11 have lengths smaller than the gate lines having the maximum length, and intersect with some data lines 12 among the plurality of data lines 12.

Abstract: Provided is a technique of suppressing display defects such as flicker, without limiting the arrangement of data lines, in a liquid crystal display device having a display area in a non-rectangular shape. A liquid crystal display device includes an active matrix substrate 10, a counter substrate, and a liquid crystal layer. The active matrix substrate 10 includes a plurality of gate lines 11, and a plurality of data lines 12. In each of pixels defined by the gate lines 11 and the data lines 12, a pixel electrode 14 is arranged, and in a display area R, common electrodes 15 are provided. Outside the display area R, capacitance-generating parts C that generate capacitances between some gate lines 11 among the plurality of gate lines 11 and the common electrode are provided. The some gate lines 11 have lengths smaller than the gate lines having the maximum length, and intersect with some data lines 12 among the plurality of data lines 12.

Abstract: A gate driving circuit includes circuits each provided in such a manner as to, as a scanning signal, select a single clock pulse of a clock signal and output the clock pulse. The circuits each include: a transistor for outputting a scanning signal; a transistor for controlling an electric potential of a gate of the transistor so that the electric potential of the gate is at a low level; a transistor for, while the transistor is not outputting the scanning signal, controlling an electric potential of a gate of the transistor so that the electric potential of the gate is at a high level; and a transistor for, while the transistor is not in operation during a period during which an operation of the selection circuit is paused, controlling the electric potential of the gate of the transistor so that the electric potential becomes high.

Abstract: By reducing the potential drop of a storage node that occurs due to feedthrough, the capacitance of a storage capacitor is reduced and sensor sensitivity is improved. In a photosensor, the first terminal of a storage capacitor (C2) and the gate of a MOS transistor (M1), which outputs a signal in accordance with the potential of a storage node (N2), are connected to the storage node (N2). A forward biased pulse voltage is supplied to the anode of a first photodiode (DS) in a reset period, and a reverse biased voltage is supplied to the anode of the first photodiode in a storage period and a readout period. A reverse biased voltage is supplied to the anode of a second photodiode (DM) in all operation periods.

Abstract: An object of the present invention is to provide a power supply circuit including a charge-pumping booster section which uses switching elements provided only by N-channel transistors yet does not have a problem of voltage drop by threshold value. In a booster section (11a), capacitors (C1) and (C2) have their respective first terminals connected with transistors (Q1, Q3) and (Q2, Q4) respectively. Each transistor has its gate terminal supplied with control signals generated in a driver section (11b). The driver section (11b) includes capacitors (C3, C4) connected with input terminals (Ti3, Ti4) for respective supply of clock signals DCK2, DCK2B each having a voltage alternating between ?VDD and VDD (VDD represents an input supply voltage from outside), as level-shifted signals of clock signals DCK1, DCK1B which are supplied to second terminals of the capacitors (C1, C2) respectively.

Abstract: A plurality of sensor circuits each including an optical sensor and a charge retention transistor each provided between a reset line and an accumulation node are arranged in a pixel region of a display device. In a sensing period, a LOW-level voltage is applied as a reset cancellation voltage to the reset line RSTa, and a HIGH-level voltage is applied to a control line CLKa to control the charge retention transistor to be in an ON state. In a period other than the sensing period, the LOW-level voltage is applied to the control line CLKa to control the charge retention transistor to be in an OFF state, and the HIGH-level voltage is applied as a retention voltage to the reset line RSTa. Thus, a drain-source voltage Vds of the charge retention transistor is lowered, a leakage current through the charge retention transistor is reduced, and a light detection accuracy is enhanced.

Abstract: Detection signals of respective photo sensor circuits (senS, senD, senON, and senOFF) are activated so as to be output at once for each group of prescribed plural number of sensor rows (LSk) by a row driver (6). Within the prescribed number of sensor rows (LSk), photo sensor circuits (senS, senD, senON, and senOFF) sharing the same power line (SL2, SL5, . . . ) between at least two different sensor rows (LSk) are included. The detection signals of the respective photo sensor circuits (senS, senD, senON, and senOFF) in the prescribed number of sensor rows (senS, senD, senON, and senOFF) are output via mutually different output lines (SL1/SL3, SL4/SL6, . . . ).

Abstract: An embodiment of the present invention provides a power supply circuit including a charge-pumping booster section which uses switching elements provided only by N-channel transistors yet does not have a problem of voltage drop by threshold value. When a boosted voltage is obtained at a first terminal of a first capacitor in a booster section, a booster control section supplies this boosted voltage to a third capacitor, to boost the voltage further thereby turning ON a first transistor. When a boosted voltage is obtained at a first terminal of a second capacitor in the booster section, the booster control section supplies this boosted voltage to a fourth capacitor, to boost the voltage further thereby turning ON a second transistor. This arrangement eliminates a problem of voltage drop by threshold value in the first and the second transistors which serve as output-side switching elements.

Abstract: The present invention aims to provide a monolithic driver-type display device capable of reducing circuit scale of a sampling circuit, and keeping low power consumption by directly driving a source driver with an externally provided video signal. In the monolithic driver-type display device having a display portion for displaying video and circuits for driving the display portion formed on the same insulating substrate, a plurality of sampling switches are provided in association with a plurality of pieces of bit data contained in externally inputted digital video signals. The sampling switches are opened/closed based on sampling signals, thereby sampling the digital video signals for each piece of the bit data and converting the signals into parallel format for output to data lines. The outputted digital video signals charge parasitic capacitances on the data lines and are held therein.

Abstract: A level shift circuit includes first and second level shifters which respectively output first and second output signals that are produced by level shifting two kinds of input clock signals whose high level periods do not overlap. The level shift circuit also includes control transistors and control lines which, together, prevent a feedthrough current from flowing into the second level shifter when the first output signal is high level, and prevent a feedthrough current from flowing into the first level shifter when the second output signal is high level, so as to suspend the level shift operation of the first and second level shifters. With the level shift circuit, power consumption during a specific time period in a non-active period of the clock signal can be eliminated, where the specific time period of one clock signal is the active period of the other clock signal.

Abstract: By reducing the potential drop of a storage node that occurs due to feedthrough, the capacitance of a storage capacitor is reduced and sensor sensitivity is improved. In a photosensor, the first terminal of a storage capacitor (C2) and the gate of a MOS transistor (M1), which outputs a signal in accordance with the potential of a storage node (N2), are connected to the storage node (N2). A forward biased pulse voltage is supplied to the anode of a first photodiode (DS) in a reset period, and a reverse biased voltage is supplied to the anode of the first photodiode in a storage period and a readout period. A reverse biased voltage is supplied to the anode of a second photodiode (DM) in all operation periods.

Abstract: An example control signal generating circuit CTL for controlling the writing into pixels PIX instructs a data signal line drive circuit SD2, which is for driving pixels in a non-display area, to write a voltage VB or a voltage VW which are for non-displaying, not only in the first frame but also once in a predetermined number of frames. In other words, the pixels in the display area are refreshed at intervals longer than those in the case of refreshing the pixels in each frame.

Abstract: A liquid crystal display apparatus (1) wherein the shift registers of a source driver (4) are configured by use of asynchronous RS flip-flops in which an active input to a set input terminal has a higher priority than an active input to a reset terminal. In a second mode of operation, first and second clock signals and a start pulse are fixed at high levels, thereby performing discharges from all the pixels (PIX) of a liquid crystal panel (2).

Abstract: An embodiment of the present invention provides a power supply circuit including a charge-pumping booster section which uses switching elements provided only by N-channel transistors yet does not have a problem of voltage drop by threshold value. When a boosted voltage is obtained at a first terminal of a first capacitor in a booster section, a booster control section supplies this boosted voltage to a third capacitor, to boost the voltage further thereby turning ON a first transistor. When a boosted voltage is obtained at a first terminal of a second capacitor in the booster section, the booster control section supplies this boosted voltage to a fourth capacitor, to boost the voltage further thereby turning ON a second transistor. This arrangement eliminates a problem of voltage drop by threshold value in the first and the second transistors which serve as output-side switching elements.

Abstract: The present invention aims to provide a monolithic driver-type display device capable of reducing circuit scale of a sampling circuit, and keeping low power consumption by directly driving a source driver with an externally provided video signal. In the monolithic driver-type display device having a display portion for displaying video and circuits for driving the display portion formed on the same insulating substrate, a plurality of sampling switches are provided in association with a plurality of pieces of bit data contained in externally inputted digital video signals. The sampling switches are opened/closed based on sampling signals, thereby sampling the digital video signals for each piece of the bit data and converting the signals into parallel format for output to data lines. The outputted digital video signals charge parasitic capacitances on the data lines and are held therein.

Abstract: An object of the present invention is to provide a power supply circuit including a charge-pumping booster section which uses switching elements provided only by N-channel transistors yet does not have a problem of voltage drop by threshold value. In a booster section (11a), capacitors (C1) and (C2) have their respective first terminals connected with transistors (Q1, Q3) and (Q2, Q4) respectively. Each transistor has its gate terminal supplied with control signals generated in a driver section (11b). The driver section (11b) includes capacitors (C3, C4) connected with input terminals (Ti3, Ti4) for respective supply of clock signals DCK2, DCK2B each having a voltage alternating between ?VDD and VDD (VDD represents an input supply voltage from outside), as level-shifted signals of clock signals DCK1, DCK1B which are supplied to second terminals of the capacitors (C1, C2) respectively.

Abstract: A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn?1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn?1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.

Abstract: A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn?1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn?1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.

Abstract: In one embodiment of the present invention, a NAND circuit, an inverter, a plurality of transistors serve as stopping devices for stopping operation of a circuit in a manner responsive to a level of an initializing signal that is fed. If the initializing signal that is Low-level is fed into the NAND circuit, then a plurality of transistors all become OFF. This makes it possible to reduce steady current flowing across a voltage and a start signal. Steady current flowing across the voltage and a start inverted signal is also reduced. Thus, the steady current flowing through the level shifter is reduced reliably, regardless of the way of use, when necessary.