Abstract: A non-volatile memory device includes an array of non-volatile memory cells. When programming the memory cells, a voltage supply source is used that includes multiple independent charge pumps. The independent charge pumps supply the programming voltage to different ones of bit lines in the array of memory cells. Using multiple charge pumps tends to reduce output voltage fluctuations and thereby reduce power loss.

Abstract: Techniques for programming a non-volatile memory device, such as a Flash memory, include floating source lines of memory cells based on a data pattern that is being programmed to the memory device. The source lines to float are selected such that a distance between drain bit lines and source bit lines of different memory cells in a row is maximized. In this manner, leakage current between these drain bit lines and source bit lines can be decreased.

Abstract: A non-volatile memory device includes an array of non-volatile memory cells. When programming the memory cells, a voltage supply source is used that includes multiple independent charge pumps. The independent charge pumps supply the programming voltage to different ones of bit lines in the array of memory cells. Using multiple charge pumps tends to reduce output voltage fluctuations and thereby reduce power loss.

Abstract: Systems and/or methods that accessing data to/from a memory are presented. A memory component can employ an optimized buffer component that can provide a single precharge control signal to facilitate precharging a bitline(s), a y-decoder component(s), an input/output line(s), and/or other lines or components associated with a buffer cell(s) in the optimized buffer component to facilitate optimized timing control associated with execution of operations to facilitate reducing errors that can be caused by charge sharing problems. The optimized buffer component can include an x-decoder component that can employ a JIT power component that can facilitate enabling a wordline associated with a buffer cell(s) only for the length of time access to the buffer cell is desired to read data therefrom or write data thereto to facilitate minimizing the access time and thereby minimize power consumption and/or thermal loading.

Abstract: Systems and/or methods that accessing data to/from a memory are presented. A memory component can employ an optimized buffer component that can provide a single precharge control signal to facilitate precharging a bitline(s), a y-decoder component(s), an input/output line(s), and/or other lines or components associated with a buffer cell(s) in the optimized buffer component to facilitate optimized timing control associated with execution of operations to facilitate reducing errors that can be caused by charge sharing problems. The optimized buffer component can include an x-decoder component that can employ a JIT power component that can facilitate enabling a wordline associated with a buffer cell(s) only for the length of time access to the buffer cell is desired to read data therefrom or write data thereto to facilitate minimizing the access time and thereby minimize power consumption and/or thermal loading.

Abstract: A method is provided for programming a nonvolatile memory device including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window that identifies a plurality of memory cells in the array. A first group of memory cells to be programmed is identified from the plurality of memory cells in the programming window. The first group of memory cells is programmed and a programming state of the first group of memory cells is verified.

Abstract: A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array and determining which of the predetermined number of bits are to be programmed in the memory array. The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array. A programming state of the predetermined number of bits in the array is simultaneously verified.

Abstract: A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element having at least two charge storage areas for storing at least two independent charges, a source region and a drain region. The method includes designating at least one memory cell as a high-speed memory cell and pre-conditioning the high-speed memory cells by placing a first of the at least two charge storage areas into a programmed state, and subsequently enabling the programming on the second area with much higher rate.

Abstract: A non-volatile memory, such as a Flash memory, is configured to perform a random multi-page read operation. The memory may include a core array of non-volatile memory cells and input lines for receiving an indication of the random multi-page read operation. Further, the memory may include a multi-level volatile memory coupled to the core array that is configured to simultaneously process multiple pages of data from the core array in a pipelined manner. Output lines are coupled to the multi-level volatile memory and output the pages of data from the memory device.

Abstract: A method is provided for programming a nonvolatile memory device including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window that identifies a plurality of memory cells in the array. A first group of memory cells to be programmed is identified from the plurality of memory cells in the programming window. The first group of memory cells is programmed and a programming state of the first group of memory cells is verified.

Abstract: A method is provided for programming a nonvolatile memory device including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window that identifies a plurality of memory cells in the array. A first group of memory cells to be programmed is identified from the plurality of memory cells in the programming window. The first group of memory cells is programmed and a programming state of the first group of memory cells is verified.

Abstract: A non-volatile memory, such as a Flash memory, is configured to perform a random multi-page read operation. The memory may include a core array of non-volatile memory cells and input lines for receiving an indication of the random multi-page read operation. Further, the memory may include a multi-level volatile memory coupled to the core array that is configured to simultaneously process multiple pages of data from the core array in a pipelined manner. Output lines are coupled to the multi-level volatile memory and output the pages of data from the memory device.

Abstract: A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array and determining which of the predetermined number of bits are to be programmed in the memory array. The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array. A programming state of the predetermined number of bits in the array is simultaneously verified.

Abstract: A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element having at least two charge storage areas for storing at least two independent charges, a source region and a drain region. The method includes designating at least one memory cell as a high-speed memory cell and pre-conditioning the high-speed memory cells by placing a first of the at least two charge storage areas into a programmed state, and subsequently enabling the programming on the second area with much higher rate.