Patents by Inventor Sachit Kadle

Sachit Kadle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12645217
    Abstract: To determine a path through a pose configuration space, trajectories of poses may be evaluated in parallel based at least on translating the trajectories along at least one axis of the pose configuration space (e.g., an orientation axis). A trajectory may include at least a portion of a turn having a fixed turn radius. Turns or turn portions that have the same turn radius and initial orientation can be translatively shifted along and processed in parallel along the orientation axis as they are translated copies of each other, but with different starting points. Trajectories may be evaluated based at least on processing variables used to evaluate reachability as bit vectors with threads effectively performing large vector operations in synchronization. A parallel reduction pattern may be used to account for dependencies that may exist between sections of a trajectory for evaluating reachability, allowing for the sections to be processed in parallel.
    Type: Grant
    Filed: October 25, 2023
    Date of Patent: June 2, 2026
    Assignee: NVIDIA Corporation
    Inventors: David Nister, Yizhou Wang, Jaikrishna Soundararajan, Sachit Kadle
  • Publication number: 20250199853
    Abstract: The present disclosure relates to executing a first task of an application over one or more first execution iterations to generate one or more first data iterations of first data. At least one individual first timestamp may respectively correspond to at least one first data iterations of the one or more first data iterations. A second task may be executed to generate one or more second data iterations based at least on the at least one first data iteration, the second task obtaining the at least one individual first timestamp corresponding to the at least one first data iteration. In some embodiments, the at least one first data iteration for use may be selected based at least on the corresponding at least one first timestamp.
    Type: Application
    Filed: December 15, 2023
    Publication date: June 19, 2025
    Inventors: Akila Damsara JAYAWARDANE, Aly HIRANI, Sachit KADLE, Christopher DANNEMILLER
  • Publication number: 20240053749
    Abstract: To determine a path through a pose configuration space, trajectories of poses may be evaluated in parallel based at least on translating the trajectories along at least one axis of the pose configuration space (e.g., an orientation axis). A trajectory may include at least a portion of a turn having a fixed turn radius. Turns or turn portions that have the same turn radius and initial orientation can be translatively shifted along and processed in parallel along the orientation axis as they are translated copies of each other, but with different starting points. Trajectories may be evaluated based at least on processing variables used to evaluate reachability as bit vectors with threads effectively performing large vector operations in synchronization. A parallel reduction pattern may be used to account for dependencies that may exist between sections of a trajectory for evaluating reachability, allowing for the sections to be processed in parallel.
    Type: Application
    Filed: October 25, 2023
    Publication date: February 15, 2024
    Inventors: David Nister, Yizhou Wang, Jaikrishna Soundararajan, Sachit Kadle
  • Patent number: 11860628
    Abstract: To determine a path through a pose configuration space, trajectories of poses may be evaluated in parallel based at least on translating the trajectories along at least one axis of the pose configuration space (e.g., an orientation axis). A trajectory may include at least a portion of a turn having a fixed turn radius. Turns or turn portions that have the same turn radius and initial orientation can be translatively shifted along and processed in parallel along the orientation axis as they are translated copies of each other, but with different starting points. Trajectories may be evaluated based at least on processing variables used to evaluate reachability as bit vectors with threads effectively performing large vector operations in synchronization. A parallel reduction pattern may be used to account for dependencies that may exist between sections of a trajectory for evaluating reachability, allowing for the sections to be processed in parallel.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: January 2, 2024
    Assignee: NVIDIA Corporation
    Inventors: David Nister, Yizhou Wang, Jaikrishna Soundararajan, Sachit Kadle
  • Publication number: 20220404829
    Abstract: To determine a path through a pose configuration space, trajectories of poses may be evaluated in parallel based at least on translating the trajectories along at least one axis of the pose configuration space (e.g., an orientation axis). A trajectory may include at least a portion of a turn having a fixed turn radius. Turns or turn portions that have the same turn radius and initial orientation can be translatively shifted along and processed in parallel along the orientation axis as they are translated copies of each other, but with different starting points. Trajectories may be evaluated based at least on processing variables used to evaluate reachability as bit vectors with threads effectively performing large vector operations in synchronization. A parallel reduction pattern may be used to account for dependencies that may exist between sections of a trajectory for evaluating reachability, allowing for the sections to be processed in parallel.
    Type: Application
    Filed: June 21, 2021
    Publication date: December 22, 2022
    Inventors: David Nister, Yizhou Wang, Jaikrishna Soundararajan, Sachit Kadle