Patents by Inventor Sachiyuki Abe

Sachiyuki Abe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10797643
    Abstract: An oscillation circuit has a charge-discharge type oscillation unit that performs an oscillation operation at an oscillating frequency that is in accordance with a control current value, and a control current generation unit that generates the control current. The control current generation unit includes a reference voltage generation circuit that generates a reference voltage that has a first temperature characteristic, a temperature characteristic slope correction circuit that corrects a slope of a temperature characteristic of a reference voltage in accordance with first correction information and generates an output voltage that has a second temperature characteristic, and a voltage-current conversion circuit that converts the output voltage of the temperature characteristic slope correction circuit into the control voltage, and that corrects the control current value in accordance with second correction information.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: October 6, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Toshikazu Kuwano, Takahiro Kikuchi, Sachiyuki Abe, Shuji Kawaguchi
  • Patent number: 10714243
    Abstract: Provided is a variable resistance circuit in which the resistance value of the variable resistance circuit can be accurately adjusted, by reducing the error in the change amount of the resistance value of the variable resistance circuit due to the on-resistances of switch circuits even if the switch circuits that each bypass a resistor included in a ladder resistor circuit are switched between an OFF state and an ON state. This variable resistance circuit includes: a ladder resistor circuit including a plurality of resistors; a first switch circuit connected in series to one end of one resistor of the plurality of resistors; and a second switch circuit connected in parallel to a series circuit of the one resistor and the first switch circuit. When one of the first and second switch circuits is turned on, the other of the first and second switch circuits is turned off.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: July 14, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Takahiro Kikuchi, Toshikazu Kuwano, Sachiyuki Abe, Shuji Kawaguchi
  • Publication number: 20190267972
    Abstract: Provided is a variable resistance circuit in which the resistance value of the variable resistance circuit can be accurately adjusted, by reducing the error in the change amount of the resistance value of the variable resistance circuit due to the on-resistances of switch circuits even if the switch circuits that each bypass a resistor included in a ladder resistor circuit are switched between an OFF state and an ON state. This variable resistance circuit includes: a ladder resistor circuit including a plurality of resistors; a first switch circuit connected in series to one end of one resistor of the plurality of resistors; and a second switch circuit connected in parallel to a series circuit of the one resistor and the first switch circuit. When one of the first and second switch circuits is turned on, the other of the first and second switch circuits is turned off.
    Type: Application
    Filed: February 25, 2019
    Publication date: August 29, 2019
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Takahiro KIKUCHI, Toshikazu KUWANO, Sachiyuki ABE, Shuji KAWAGUCHI
  • Publication number: 20190199287
    Abstract: An oscillation circuit has a charge-discharge type oscillation unit that performs an oscillation operation at an oscillating frequency that is in accordance with a control current value, and a control current generation unit that generates the control current. The control current generation unit includes a reference voltage generation circuit that generates a reference voltage that has a first temperature characteristic, a temperature characteristic slope correction circuit that corrects a slope of a temperature characteristic of a reference voltage in accordance with first correction information and generates an output voltage that has a second temperature characteristic, and a voltage-current conversion circuit that converts the output voltage of the temperature characteristic slope correction circuit into the control voltage, and that corrects the control current value in accordance with second correction information.
    Type: Application
    Filed: December 26, 2018
    Publication date: June 27, 2019
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Toshikazu KUWANO, Takahiro KIKUCHI, Sachiyuki ABE, Shuji KAWAGUCHI
  • Patent number: 10152937
    Abstract: This semiconductor device includes a first regulator that stabilizes an input voltage to generate a stabilized voltage; a voltage boosting circuit that boosts the stabilized voltage to generate a boosted voltage; a second regulator that stabilizes the boosted voltage to generate a first power supply voltage; and a third regulator that is connected to the second regulator in parallel, and that stabilizes the boosted voltage to generate a second power supply voltage.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: December 11, 2018
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Sachiyuki Abe, Nobuyuki Oikawa
  • Patent number: 10031544
    Abstract: A power supply voltage detection circuit can detect the power supply voltage obtained by stabilizing a power supply voltage supplied from outside and also the magnitude of the power supply voltage before being stabilized. This power supply voltage detection circuit includes a selection circuit that selects one power supply potential from among a plurality of power supply potentials including a first power supply potential supplied from outside and a second power supply potential obtained by stabilizing the first power supply potential, a variable voltage dividing circuit that divides the voltage between the power supply potential selected by the selection circuit and a reference potential by a set division ratio, a comparison voltage generation circuit that generates a comparison voltage based on a reference voltage, and a comparator that compares the voltage divided by the variable voltage dividing circuit with the comparison voltage and outputs a signal representing a comparison result.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: July 24, 2018
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Sachiyuki Abe
  • Publication number: 20180061342
    Abstract: This semiconductor device includes a first regulator that stabilizes an input voltage to generate a stabilized voltage; a voltage boosting circuit that boosts the stabilized voltage to generate a boosted voltage; a second regulator that stabilizes the boosted voltage to generate a first power supply voltage; and a third regulator that is connected to the second regulator in parallel, and that stabilizes the boosted voltage to generate a second power supply voltage.
    Type: Application
    Filed: August 21, 2017
    Publication date: March 1, 2018
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Sachiyuki ABE, Nobuyuki OIKAWA
  • Publication number: 20160378129
    Abstract: A power supply voltage detection circuit can detect the power supply voltage obtained by stabilizing a power supply voltage supplied from outside and also the magnitude of the power supply voltage before being stabilized. This power supply voltage detection circuit includes a selection circuit that selects one power supply potential from among a plurality of power supply potentials including a first power supply potential supplied from outside and a second power supply potential obtained by stabilizing the first power supply potential, a variable voltage dividing circuit that divides the voltage between the power supply potential selected by the selection circuit and a reference potential by a set division ratio, a comparison voltage generation circuit that generates a comparison voltage based on a reference voltage, and a comparator that compares the voltage divided by the variable voltage dividing circuit with the comparison voltage and outputs a signal representing a comparison result.
    Type: Application
    Filed: June 3, 2016
    Publication date: December 29, 2016
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Sachiyuki ABE
  • Patent number: 5376825
    Abstract: A single-packaged central processing unit (CPU) is formed on a substrate for a particular application in a variable word length computer system that includes a program memory. A first semiconductor chip in the CPU is of a general purpose type and includes a plurality of elements interconnected, such as an arithmetic logic unit (ALU), a program counter, and a register. A second semiconductor chip in the CPU is mounted on the first semiconductor chip with their active surfaces facing each other. The second semiconductor chip is configured for the particular application in accordance with a particular program instruction set stored in the program memory. The second semiconductor chip includes a command register for receiving fetched commands from the program memory, a command decoder for decoding the fetched commands and for generating corresponding control signals, and a timing generator for generating system clock signals.
    Type: Grant
    Filed: November 18, 1993
    Date of Patent: December 27, 1994
    Assignee: Seiko Epson Corporation
    Inventors: Takashi Tukamoto, Sachiyuki Abe, Tetsuo Yabushita, Yoshimitsu Hayashi
  • Patent number: 5309560
    Abstract: A data selection device having M+1 stages. Each stage has stored therein prioritized data. Selection of the highest prioritized data available at any instant in time is based on a comparison repeated M times of both the selectability and priority of data available from two different stages of the device. The highest prioritized data is provided at the output of the M+1 stage.
    Type: Grant
    Filed: October 13, 1992
    Date of Patent: May 3, 1994
    Assignee: Seiko Epson Corporation
    Inventors: Sachiyuki Abe, Hisao Sato, Hiroaki Nasu, Yasuaki Hagiwara
  • Patent number: 5126695
    Abstract: A semiconductor integrated circuit device comprises a first oscillator circuit driven by a first voltage for generating a first clock signal employed as the internal system clock signal for an internal circuit in the integrated circuit device and a second oscillator circuit driven by a second voltage lower than said first voltage for generating a second clock signal. A voltage boost circuit generates a stepped up voltage based on the second clock signal, which stepped up voltage is higher than the first voltage and is supplied to the first oscillator circuit and the internal circuit as their circuit source voltage.
    Type: Grant
    Filed: March 1, 1991
    Date of Patent: June 30, 1992
    Assignee: Seiko Epson Corporation
    Inventor: Sachiyuki Abe