Patents by Inventor Sachiyuki Nose

Sachiyuki Nose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6772511
    Abstract: A semiconductor device includes a circuit board, a semiconductor element that is mounted on an upper surface of the circuit board and has an electrode terminal, and a sealing resin for sealing a periphery of the semiconductor element that is mounted on the upper surface of the circuit board. The circuit board includes a plurality of conductive members and an insulating substance for binding and fixing the plurality of conductive members. Each of the plurality of conductive members includes a conductive material formed integrally from the upper surface through the lower surface of the circuit board, and an insulating material covering an outer circumference of the conductive material. The conductive material of at least one conductive member of the plurality of conductive members is exposed to the upper surface of the circuit board.
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: August 10, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Sachiyuki Nose
  • Patent number: 6707158
    Abstract: A semiconductor device includes a circuit board, a semiconductor element that is mounted on an upper surface of the circuit board and has an electrode terminal, and a sealing resin for sealing a periphery of the semiconductor element that is mounted on the upper surface of the circuit board. The circuit board includes a plurality of conductive members and an insulating substance for binding and fixing the plurality of conductive members. Each of the plurality of conductive members includes a conductive material formed integrally from the upper surface through the lower surface of the circuit board, and an insulating material covering an outer circumference of the conductive material. The conductive material of at least one conductive member of the plurality of conductive members is exposed to the upper surface of the circuit board.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: March 16, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Sachiyuki Nose
  • Publication number: 20030110622
    Abstract: A semiconductor device includes a circuit board, a semiconductor element that is mounted on an upper surface of the circuit board and has an electrode terminal, and a sealing resin for sealing a periphery of the semiconductor element that is mounted on the upper surface of the circuit board. The circuit board includes a plurality of conductive members and an insulating substance for binding and fixing the plurality of conductive members. Each of the plurality of conductive members includes a conductive material formed integrally from the upper surface through the lower surface of the circuit board, and an insulating material covering an outer circumference of the conductive material. The conductive material of at least one conductive member of the plurality of conductive members is exposed to the upper surface of the circuit board.
    Type: Application
    Filed: January 24, 2003
    Publication date: June 19, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventor: Sachiyuki Nose
  • Publication number: 20020132450
    Abstract: A semiconductor device includes a circuit board, a semiconductor element that is mounted on an upper surface of the circuit board and has an electrode terminal, and a sealing resin for sealing a periphery of the semiconductor element that is mounted on the upper surface of the circuit board. The circuit board includes a plurality of conductive members and an insulating substance for binding and fixing the plurality of conductive members. Each of the plurality of conductive members includes a conductive material formed integrally from the upper surface through the lower surface of the circuit board, and an insulating material covering an outer circumference of the conductive material. The conductive material of at least one conductive member of the plurality of conductive members is exposed to the upper surface of the circuit board.
    Type: Application
    Filed: March 13, 2002
    Publication date: September 19, 2002
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventor: Sachiyuki Nose
  • Patent number: 6040621
    Abstract: A semiconductor device is provided with a wiring body including an insulating supporting substrate, and signal lines, power lines and ground lines printed on first and second surfaces of the insulating supporting substrate. The wiring body is mounted on a semiconductor chip, inside pads of the lines of the wiring body are connected with bonding pads on the semiconductor chip through first metal lines, and outside pads of the lines are connected with leads of a lead frame. Since the wiring body has a structure in which the lines are supported by the insulating supporting substrate, refined and various line patterns can be formed by using the wiring body, and an impedance matching function can also be attained. Thus, the invention provides a semiconductor device which can exhibit high noise resistance for a high frequency signal and a high operation speed and a wiring body to be disposed in a high frequency circuit.
    Type: Grant
    Filed: March 23, 1998
    Date of Patent: March 21, 2000
    Assignee: Matsushita Electronics Corporation
    Inventor: Sachiyuki Nose
  • Patent number: 5817208
    Abstract: The present invention intends to improve the productivity and reliability of a resin-sealed-type semiconductor device. Therefore, the invention provides a resin sealing die for integrally molding a semiconductor chip, a lead frame to which the semiconductor chip is fixed, and metal wires which electrically connect the electrode terminals of the semiconductor chip to the inner leads of a head frame with sealing resin to manufacture a resin-sealed-type semiconductor device, wherein a cavity of the resin sealing die is formed at a portion where separable upper and lower dies confront each other, at least one of the upper surface of the cavity of the upper die and the lower surface of the cavity of the lower die comprises an engraved hole, and a metal block having a mark carved on a reference surface thereof facing the cavity is detachably attached to the engraved hole.
    Type: Grant
    Filed: August 1, 1996
    Date of Patent: October 6, 1998
    Assignee: Matsushita Electronics Corporation
    Inventors: Sachiyuki Nose, Minako Onoe
  • Patent number: 5397915
    Abstract: A semiconductor element mounting die pad is supported by tie bars. Plural slits and dimples are disposed on a flat surface. The slits are penetrating from the face to the back side of the semiconductor element mounting die pad. Slits are formed, for example, by a punching or chemical etching method. These forming methods are the same as the method of forming the lead frame. Accordingly, if slits are disposed simultaneously when forming the lead frame, the process is not complicated. It is also possible to form these slits using the prior art. Slits of the same shape are formed at an interval of the width of dimples. The rear side is pushed out by press means to form dimples with the boundary of the slits. Thus, slits are formed in one body at both ends of the dimples. By thus composing, the thin type surface mount semiconductor device has a sufficient mechanical strength, and is capable of controlling the stress in a narrow region, so that a semiconductor device of high reliability is realized.
    Type: Grant
    Filed: February 12, 1992
    Date of Patent: March 14, 1995
    Assignee: Matsushita Electronics Corporation
    Inventor: Sachiyuki Nose