Abstract: A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.

Abstract: A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.

Abstract: A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.

Abstract: A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.

Abstract: A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.

Abstract: A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.

Abstract: A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.

Abstract: In a method of forming MOS transistor, a gate structure is formed on a substrate and a first spacer layer is formed on the substrate conformal to the gate structure. A second spacer layer is formed on the first spacer layer. A second spacer is formed on the first spacer layer corresponding to a sidewall of the gate structure by partially removing the second spacer layer from the first spacer layer. Impurities are implanted in the substrate by an ion implantation process using the gate structure including the first spacer layer and the second spacer as an ion implantation mask to form source/drain extension regions at surface portions of the substrate around the gate structure.

Abstract: In a method of forming MOS transistor, a gate structure is formed on a substrate and a first spacer layer is formed on the substrate conformal to the gate structure. A second spacer layer is formed on the first spacer layer. A second spacer is formed on the first spacer layer corresponding to a sidewall of the gate structure by partially removing the second spacer layer from the first spacer layer. Impurities are implanted in the substrate by an ion implantation process using the gate structure including the first spacer layer and the second spacer as an ion implantation mask to form source/drain extension regions at surface portions of the substrate around the gate structure.

Abstract: The present invention provides a semiconductor device comprising a capacitive element with a very uniform capacitive value as well as a method of manufacturing the semiconductor device. In a capacitive element formation region 20 of a semiconductor device 1, an N-type well 22 as a conductive layer is formed in a surface layer of a P-type semiconductor substrate 10. A capacitive film 24 is deposited on a front surface of the semiconductor substrate 10 on which the N-type well 22 is formed. The part of front surface of the semiconductor substrate 10 in which the capacitive film 24 is deposited is substantially flat. An upper electrode 26 is provided on the capacitive film 24. The upper electrode 26 constitutes a capacitive element (on-chip capacitor) together with the N-type well 22, located opposite the upper electrode 26 across the capacitive film 24.

Abstract: The present invention is to provide a high-quality semiconductor device allowing independent control of threshold voltage values of gate electrodes of transistors which reside in a plurality of one-conductivity-type regions and in a reverse-conductivity-type region. The semiconductor comprises a P-type Si substrate 109, a plurality of P-type wells 103a, 103b connected to each other via the bottom surface side of the P-type Si substrate 109, and an N-type well 101 provided so as to surround side portions of the plurality of P-type wells 103a, 103b. The semiconductor device also has NMOS transistors 107a, 107b provided on the P-type wells 103a, 103b, and PMOS transistors 105a, 105b, 105c provided on the N-type well 101. The semiconductor device still also has an N-type well 133 provided just under the N-type well 101 and connected therewith.

Abstract: There is provided a semiconductor device in which the thresholds of gate electrodes in transistors can be adjusted together for each of regions having their own functions different from one another. The semiconductor device is provided with: a P-type Si substrate 109; a P-type annular well 181 provided in the element formation surface side of the P-type Si substrate 109; and a N-type annular well 183 provided inside the P-type annular well 181. Moreover, an SRAM-P-type well 185 and an SRAM-N-type well 189 are provided inside the N-type annular well 183. A deep N-type well 133 is provided nearer to the bottom side of the P-type Si substrate 109 than the SRAM-P-type well 185 and the SRAM-N-type well 189. A plurality of P-type wells 103 are provided outside the P-type annular well 181, and a N-type 101 is provided in such a way that the well 101 encloses the outside faces of the P-type wells 103.

Abstract: There is provided a semiconductor device in which the thresholds of gate electrodes in transistors can be adjusted together for each of regions having their own functions different from one another. The semiconductor device is provided with: a P-type Si substrate 109; a P-type annular well 181 provided in the element formation surface side of the P-type Si substrate 109; and a N-type annular well 183 provided inside the P-type annular well 181. Moreover, an SRAM-P-type well 185 and an SRAM-N-type well 189 are provided inside the N-type annular well 183. A deep N-type well 133 is provided nearer to the bottom side of the P-type Si substrate 109 than the SRAM-P-type well 185 and the SRAM-N-type well 189. A plurality of P-type wells 103 are provided outside the P-type annular well 181, and a N-type 101 is provided in such a way that the well 101 encloses the outside faces of the P-type wells 103.

Abstract: The present invention is to provide a high-quality semiconductor device allowing independent control of threshold voltage values of gate electrodes of transistors which reside in a plurality of one-conductivity-type regions and in a reverse-conductivity-type region. The semiconductor comprises a P-type Si substrate 109, a plurality of P-type wells 103a, 103b connected to each other via the bottom surface side of the P-type Si substrate 109, and an N-type well 101 provided so as to surround side portions of the plurality of P-type wells 103a, 103b. The semiconductor device also has NMOS transistors 107a, 107b provided on the P-type wells 103a, 103b, and PMOS transistors 105a, 105b, 105c provided on the N-type well 101. The semiconductor device still also has an N-type well 133 provided just under the N-type well 101 and connected therewith.

Abstract: The present invention provides a semiconductor device comprising a capacitive element with a very uniform capacitive value as well as a method of manufacturing the semiconductor device. In a capacitive element formation region 20 of a semiconductor device 1, an N-type well 22 as a conductive layer is formed in a surface layer of a P-type semiconductor substrate 10. A capacitive film 24 is deposited on a front surface of the semiconductor substrate 10 on which the N-type well 22 is formed. The part of front surface of the semiconductor substrate 10 in which the capacitive film 24 is deposited is substantially flat. An upper electrode 26 is provided on the capacitive film 24. The upper electrode 26 constitutes a capacitive element (on-chip capacitor) together with the N-type well 22, located opposite the upper electrode 26 across the capacitive film 24.

Abstract: A method for forming three gate oxide films having different thickness in first through third circuit areas, respectively. The method includes the consecutive steps of forming a first gate oxide film having a largest thickness in all the areas, removing the first gate oxide film and forming a second gate oxide film having a second largest thickness in the second circuit area, and removing the first gate oxide and forming a third gate oxide film having a smallest thickness in the third circuit area. The resultant gate oxide films have accurate thicknesses.

Abstract: A method for forming three gate oxide films having different thicknesses in first through third circuit areas, respectively. The method includes the consecutive steps of forming a first gate oxide film having a largest thickness in all the areas, removing the first gate oxide film and forming a second gate oxide film having a second largest thickness in the second circuit area, and removing the first gate oxide and forming a third gate oxide film having a smallest thickness in the third circuit area. The resultant gate oxide films have accurate thicknesses.

Abstract: A protection circuit portion comprises a CMOS to which the drain of the nMOS transistor and the pMOS transistor are connected. The drain is connected to the input or output terminal. In the nMOS transistor, the gate insulating film and the gate electrode are formed on the substrate, and the source and the drain diffusion layer are formed on the surface of the substrate at a location sandwiching the gate electrode. A P-type channel layer diffusion layer connected to the source and the drain diffusion layer is selectively formed on a lower portion of the region constituting a channel. In the pMOS, the gate insulating film, the gate electrode and the source and drain diffusion layer are formed on the well layer formed on the surface of the substrate in the same manner as the nMOS, and a channel diffusion layer is formed on the entire region of the well layer on a lower portion of the region which constitutes the channel.

Abstract: A core section complementary transistor and a memory cell section complementary transistor are formed on a semiconductor substrate of a first conductivity type. The core section complementary transistor has a first well of a second conductivity type provided in the semiconductor substrate, a first core section MOS transistor provided on the first well of the second conductivity type, a second core section MOS transistor provided on the semiconductor substrate a device separation film which separates the first core section MOS transistor and the second core section MOS transistor from each other, and a well of the first conductivity type provided under a part of the device separation film which is closer to the second core section MOS transistor. The first core section MOS transistor has source-drain regions of the first conductivity type. The second core section MOS transistor has source-drain regions of the second conductivity type.

Abstract: A method for forming three gate oxide films having different thicknesses in first through third circuit areas, respectively. The method includes the consecutive steps of forming a first gate oxide film having a largest thickness in all the areas, removing the first gate oxide film and forming a second gate oxide film having a second largest thickness in the second circuit area, and removing the first gate oxide and forming a third gate oxide film having a smallest thickness in the third circuit area. The resultant gate oxide films have accurate thicknesses.