Abstract: In a digital broadcast receiving apparatus, digital broadcast signals provided by a digital broadcast method are supplied to various types of external units and are effectively utilized. In the above apparatus, a descrambler descrambles a transport stream output from a front end unit and supplies it to a digital interface and a demultiplexer. The demultiplexer extracts from the transport stream a compressed video signal and a compressed audio signal of a program specified by a user, and supplies the extracted signals to an MPEG decoder. The MPEG decoder decompresses the supplied video signal and the audio signal and supplies them to the digital interface, an NTSC encoder, and an audio signal D/A converter. The digital interface supplies either of the transport stream or the decompressed data to a digital external unit under the control of the controller.

Abstract: In a digital broadcast receiving apparatus, digital broadcast signals provided by a digital broadcast method are supplied to various types of external units and are effectively utilized. In the above apparatus, a descrambler descrambles a transport stream output from a front end unit and supplies it to a digital interface and a demultiplexer. The demultiplexer extracts from the transport stream a compressed video signal and a compressed audio signal of a program specified by a user, and supplies the extracted signals to an MPEG decoder. The MPEG decoder decompresses the supplied video signal and the audio signal and supplies them to the digital interface, an NTSC encoder, and an audio signal D/A converter. The digital interface supplies either of the transport stream or the decompressed data to a digital external unit under the control of the controller.

Abstract: A signal processing circuit capable of preventing illicit copies, preventing the circuit from being unable to discriminate a plurality of cipher mode and unable to decipher, and correctly decipher received data at the reception side, configured to be provided with a cipher mode continuity discrimination circuit which confirms the continuity of a cipher mode at the time of reading transmission data from an FIFO when transmitting a plurality of packets, stops the transmission when a discontinuity is confirmed even if there is room in a band enabling transmission in the transmission cycle of the 1394 standard, and instructs a link core to transmit the packet enciphered by a different cipher key at the next cycle, so that only the data enciphered by one cipher mode is transmitted within one cycle of the 1394 standards, and the data enciphered by a different cipher mode is transmitted in the next cycle.

Abstract: In a digital broadcast receiving apparatus, digital broadcast signals provided by a digital broadcast method are supplied to various types of external units and are effectively utilized. In the above apparatus, a descrambler descrambles a transport stream output from a front end unit and supplies it to a digital interface and a demultiplexer. The demultiplexer extracts from the transport stream a compressed video signal and a compressed audio signal of a program specified by a user, and supplies the extracted signals to an MPEG decoder. The MPEG decoder decompresses the supplied video signal and the audio signal and supplies them to the digital interface, an NTSC encoder, and an audio signal D/A converter. The digital interface supplies either of the transport stream or the decompressed data to a digital external unit under the control of the controller.

Abstract: In a digital broadcast receiving apparatus, digital broadcast signals provided by a digital broadcast method are supplied to various types of external units and are effectively utilized. In the above apparatus, a descrambler descrambles a transport stream output from a front end unit and supplies it to a digital interface and a demultiplexer. The demultiplexer extracts from the transport stream a compressed video signal and a compressed audio signal of a program specified by a user, and supplies the extracted signals to an MPEG decoder. The MPEG decoder decompresses the supplied video signal and the audio signal and supplies them to the digital interface, an NTSC encoder, and an audio signal D/A converter. The digital interface supplies either of the transport stream or the decompressed data to a digital external unit under the control of the controller.

Abstract: A signal processing circuit which enables an error bit to be set simply without causing an increase in the size of the circuit even if the packet size is changed and which enables realization of stable operation without the system stopping even if the value of the time stamp is impossible. A pre-reception processing circuit decides if a received packet is normally continuous or discontinuous from data in the DBC region of the CIP header. When deciding it is discontinuous, it sets an error bit ERM allocated to one bit of the upper significant 7 bits of the source packet header to “1”, and writes this in an FIFO. A post-reception processing circuit, when reading from the FIFO, outputs the data stored in the FIFO to the application side when the error bit ERM is “0” and resets the error bit and outputs a dummy error packet when the error bit EMR is “1”.

Abstract: A signal processing circuit which can effectively use a serial interface bus, provided with transmission processing circuits and a link core for dividing or synthesizing an input transport stream packet based on a number of divided blocks or a number of synthesized packets set in advance in accordance with the input rate, adding a time stamp which suppresses jitter at the serial interface bus and determines the output time of the data at the reception side, and sends the same to the serial interface bus.

Abstract: A signal processing circuit which enables an error bit to be set simply without causing an increase in the size of the circuit even if the packet size is changed and which enables realization of stable operation without the system stopping even if the value of the time stamp is impossible. A pre-reception processing circuit decides if a received packet is normally continuous or discontinuous from data in the DBC region of the CIP header. When deciding it is discontinuous, it sets an error bit ERM allocated to one bit of the upper significant 7 bits of the source packet header to “1”, and writes this in an FIFO. A post-reception processing circuit, when reading from the FIFO, outputs the data stored in the FIFO to the application side when the error bit ERM is “0” and resets the error bit and outputs a dummy error packet when the error bit EMR is “1”.

Abstract: An apparatus for imprinting the raised indicia from a credit card on a copy sheet has a support provided with a holder for the credit card. A printing head is movable on the support between a raised position spaced from the holder and a lowered position juxtaposed therewith. In this lowered position an electrical actuator in the head can roll a platen roller across the card to imprint indicia on the card on a copy sheet overlying the card. An electromagnet in the support holds the head in the lowered position during the printing cycle. Switches are provided to energize the actuator once the head is fully in the lowered position and to deenergize the holding electromagnet after the printing cycle is completed so that the head can return to the raised position.