Patents by Inventor Sadahiro KATOU

Sadahiro KATOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140008615
    Abstract: A semiconductor device includes a substrate, a channel layer that is formed above the substrate, where the channel layer is made of a first nitride series compound semiconductor, a barrier layer that is formed on the channel layer, a first electrode that is formed on the barrier layer, and a second electrode that is formed above the channel layer. Here, the barrier layer includes a block layers and a quantum level layer. The block layer is formed on the channel layer and made of a second nitride series compound semiconductor having a larger band gap energy than the first nitride series compound semiconductor, and the quantum level layer is made of a third nitride series compound semiconductor having a smaller band gap energy than the second nitride series compound semiconductor, and has a quantum level formed therein.
    Type: Application
    Filed: July 28, 2013
    Publication date: January 9, 2014
    Applicant: ADVANCED POWER DEVICE RESEARCH ASSOCIATION
    Inventors: Makoto UTSUMI, Sadahiro KATOU, Masayuki IWAMI, Takuya KOKAWA
  • Publication number: 20130328106
    Abstract: Provided are a nitride-based semiconductor element with reduced leak current, and a manufacturing method thereof. The semiconductor element comprises a substrate; a buffer region that is formed above the substrate; an active layer that is formed on the buffer region; and at least two electrodes that are formed on the active layer. The buffer region includes a plurality of semiconductor layers having different lattice constants, and there is a substantially constant electrostatic capacitance between a bottom surface of the substrate and a top surface of the buffer region when a potential that is less than a potential of the bottom surface of the substrate is applied to the top surface of the buffer region and a voltage between the bottom surface of the substrate and the top surface of the buffer region is changed within a range corresponding to thickness of the buffer region.
    Type: Application
    Filed: August 13, 2013
    Publication date: December 12, 2013
    Applicant: Advanced Power Device Research Association
    Inventors: Takuya KOKAWA, Sadahiro KATOU, Masayuki IWAMI, Makato UTSUMI, Kazuyuki UMENO
  • Publication number: 20130307024
    Abstract: Provided is a semiconductor device that includes a substrate, a first buffer region formed over the substrate, a second buffer region formed on the first buffer region, an active layer formed on the second buffer region, and at least two electrodes formed on the active layer. The first buffer region includes at least one composite layer in which a first semiconductor layer and a second semiconductor layer are sequentially stacked. The second buffer region in includes at least one composite layer in which a third semiconductor layer, a fourth semiconductor layer, and a fifth semiconductor layer are sequentially stacked. The fourth lattice constant has a value between the third lattice constant and the fifth lattice constant.
    Type: Application
    Filed: July 28, 2013
    Publication date: November 21, 2013
    Applicant: ADVANCED POWER DEVICE RESEARCH ASSOCIATION
    Inventors: Takuya KOKAWA, Sadahiro KATOU, Masayuki IWAMI, Makoto UTSUMI
  • Publication number: 20130307023
    Abstract: Provided is a semiconductor device that has a buffer layer with which a dislocation density is decreased. The semiconductor device includes a substrate, a buffer region formed over the substrate, an active layer formed on the buffer region, and at least two electrodes formed on the active layer. The buffer region includes at least one composite layer in which a first semiconductor layer having a first lattice constant, a second semiconductor layer having a second lattice constant that is different from the first lattice constant and formed in contact with the first semiconductor layer, and a third semiconductor layer having a third lattice constant that is between the first lattice constant and the second lattice constant are sequentially laminated.
    Type: Application
    Filed: July 28, 2013
    Publication date: November 21, 2013
    Applicant: ADVANCED POWER DEVICE RESEARCH ASSOCIATION
    Inventors: Takuya KOKAWA, Sadahiro KATOU, Masayuki IWAMI, Makoto UTSUMI
  • Publication number: 20130306980
    Abstract: A nitride semiconductor device includes a substrate, an electron transit layer and an electron supply layer that are sequentially formed above the substrate, where the electron supply layer has a different band gap energy than the electron transit layer, a drain electrode, a gate electrode, and a source electrode that is formed on the opposite side of the drain electrode with the gate electrode being sandwiched between the drain electrode and the source electrode. Here, a plurality of lower concentration regions are formed so as to be spaced away from each other on the surface of the electron transit layer between the gate electrode and the drain electrode. In the lower concentration regions, the concentration of a two-dimensional electron gas is lower than in other regions.
    Type: Application
    Filed: July 28, 2013
    Publication date: November 21, 2013
    Applicant: ADVANCED POWER DEVICE RESEARCH ASSOCIATION
    Inventors: Yuki NIIYAMA, Jiang LI, Sadahiro KATOU