Patents by Inventor Sadahiro Nonoyama

Sadahiro Nonoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8738347
    Abstract: A method for extracting an accurate IBIS simulation model of a semiconductor device including a plurality of semiconductor chips comprises: extracting an AC characteristics model of a first output buffer in an IBIS simulation model by treating first and second output buffers of first and second semiconductor chips connected to a single external connection terminal as a transistor model and executing a transistor-level circuit simulation; calculating an output capacitance model of the first output buffer as an IBIS simulation model by adding output capacitances of the first and second output buffers as a transistor-level circuit simulation model; and synthesizing an IBIS simulation model of the first output buffer viewed from the external connection terminal by using the AC characteristics model and the output capacitance model.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: May 27, 2014
    Inventors: Tadaaki Yoshimura, Yoji Nishio, Sadahiro Nonoyama, Koji Matsuo, Shinji Itano, Yoshiyuki Yagami
  • Publication number: 20120191437
    Abstract: A method for extracting an accurate IBIS simulation model of a semiconductor device including a plurality of semiconductor chips comprises: extracting an AC characteristics model of a first output buffer in an IBIS simulation model by treating first and second output buffers of first and second semiconductor chips connected to a single external connection terminal as a transistor model and executing a transistor-level circuit simulation; calculating an output capacitance model of the first output buffer as an IBIS simulation model by adding output capacitances of the first and second output buffers as a transistor-level circuit simulation model; and synthesizing an IBIS simulation model of the first output buffer viewed from the external connection terminal by using the AC characteristics model and the output capacitance model.
    Type: Application
    Filed: January 19, 2012
    Publication date: July 26, 2012
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Tadaaki YOSHIMURA, Yoji NISHIO, Sadahiro NONOYAMA, Koji MATSUO, Shinji ITANO, Yoshiyuki YAGAMI
  • Publication number: 20080040081
    Abstract: In the simulation method of the present invention; one parameter is first selected from a plurality of parameters that relate to input/output characteristics. Next, regarding setting lines provided in a file for setting necessary choices from among a plurality of choices for a selected parameter, it is determined to either set choices by means of comment symbols that cause non-execution of the relevant lines, or set choices by means of identification codes, which are identifiers common to chips in which the same choice are to be set. When choices are to be set by means of comment symbols, the comment symbols of the setting lines of the necessary choices among the plurality of choices are deleted to make these setting lines effective. Alternatively, when choices are to be set by means of identification codes, the identification codes included in setting lines are rewritten to information for setting to the necessary choices. Finally, the simulation is executed.
    Type: Application
    Filed: February 16, 2007
    Publication date: February 14, 2008
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Yoji NISHIO, Seiji Funaba, Yurika Aoki, Kazuyoshi Shoji, Koji Matsuo, Mariko Otsuka, Ryuichi Ikematsu, Sadahiro Nonoyama, Kae Fujii