Patents by Inventor Sadaki Nakano

Sadaki Nakano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040000713
    Abstract: Disclosed here is a semiconductor device employable for a compact and light sensor system free of battery replacement. The semiconductor device configures a sensor chip (SCHIP1) comprising sensors (TD1, AS1, PD1, GS1), an A/D conversion circuit (AD1), a microprocessor (CPU1), a memory (MEM1), a transmission circuit (RF1), and a power generation circuit (CM1). The sensors, the A/D conversion circuit, the microprocessor, the memory, and the transmission circuit are formed on one side (SIDE1) of the substrate while the power generation unit is formed on the other side (SIDE2) of the substrate.
    Type: Application
    Filed: June 10, 2003
    Publication date: January 1, 2004
    Inventors: Shunzo Yamashita, Kei Suzuki, Toshiyuki Aritsuka, Masayuki Miyazaki, Sadaki Nakano
  • Patent number: 5918045
    Abstract: The data processor includes a CPU and an instruction prefetch buffer that prefetches an instruction executed by the CPU and stores it therein. The CPU contains a detection circuit for detecting whether or not a displacement from a branch instruction to a branch target instruction is a specific displacement on the basis of branch displacement information that the concerned branch instruction holds. The instruction prefetch buffer clears an instruction already prefetched when the detection circuit detects that the displacement is not the specific displacement and outputs a branch target instruction newly fetched to the CPU, and outputs a branch target instruction already prefetched to the CPU when the detection circuit detects that the displacement is the specific displacement. Thus, the date processor fetches a branch target instruction within a certain range from the instruction prefetch buffer at a high speed without adding the nullifying bit on the instruction code.
    Type: Grant
    Filed: October 17, 1997
    Date of Patent: June 29, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Osamu Nishii, Sadaki Nakano, Norio Nakagawa, Takanobu Tsunoda