Patents by Inventor Sadamasa Fujii

Sadamasa Fujii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8604627
    Abstract: The present invention aims at providing a semiconductor device capable of reliably preventing a wire bonded to an island from being disconnected due to a thermal shock, a temperature cycle and the like in mounting and capable of preventing remarkable increase in the process time. In the semiconductor device according to the present invention, a semiconductor chip is die-bonded to the surface of an island, one end of a first wire is wire-bonded to an electrode formed on the surface of the semiconductor chip to form a first bonding section and the other end of the first wire is wire-bonded to the island to form a second bonding section, while the semiconductor device is resin-sealed. A double bonding section formed by wire-bonding a second wire is provided on the second bonding section of the first wire wire-bonded onto the island.
    Type: Grant
    Filed: April 14, 2006
    Date of Patent: December 10, 2013
    Assignee: Rohm Co., Ltd.
    Inventors: Hideki Hiromoto, Sadamasa Fujii, Tsunemori Yamaguchi
  • Patent number: 8022532
    Abstract: An interposer and a semiconductor device including the interposer, which can prevent thermal warpage of an insulative substrate. The interposer is provided with a semiconductor chip in a semiconductor device and may be disposed between the semiconductor chip and a mount board. The interposer includes: a substrate of an insulative resin; an island on one surface of the substrate to be bonded to a rear surface of the chip; a thermal pad on the other surface opposite the one surface opposed to the island with the intervention of the substrate; and a thermal via extending through the substrate from the one surface to the other surface to thermally connect the island to the thermal pad.
    Type: Grant
    Filed: June 2, 2006
    Date of Patent: September 20, 2011
    Assignee: Rohm Co., Ltd.
    Inventors: Yasumasa Kasuya, Sadamasa Fujii, Motoharu Haga
  • Publication number: 20110156226
    Abstract: An interposer and a semiconductor device including the interposer are provided, which can prevent thermal warpage of an insulative substrate thereof. The interposer is provided with a semiconductor chip in a semiconductor device andmay be disposed between the semiconductor chip and a mount board. The interposer includes: a substrate of an insulative resin; an island on one surface of the substrate to be bonded to a rear surface of the chip; a thermal pad on the other surface opposite the one surface opposed to the island with the intervention of the substrate; and a thermal via extending through the substrate from the one surface to the other surface to thermally connect the island to the thermal pad.
    Type: Application
    Filed: March 9, 2011
    Publication date: June 30, 2011
    Applicant: ROHM CO., LTD.
    Inventors: Yasumasa KASUYA, Sadamasa FUJII, Motoharu HAGA
  • Patent number: 7923834
    Abstract: An interposer and a semiconductor device including the interposer, which can prevent thermal warpage of an insulative substrate. The interposer is provided with a semiconductor chip in a semiconductor device and may be disposed between the semiconductor chip and a mount board. The interposer includes: a substrate of an insulative resin; an island on one surface of the substrate to be bonded to a rear surface of the chip; a thermal pad on the other surface opposite the one surface opposed to the island with the intervention of the substrate; and a thermal via extending through the substrate from the one surface to the other surface to thermally connect the island to the thermal pad.
    Type: Grant
    Filed: June 2, 2006
    Date of Patent: April 12, 2011
    Assignee: ROHM Co., Ltd.
    Inventors: Yasumasa Kasuya, Sadamasa Fujii, Motoharu Haga
  • Publication number: 20100001413
    Abstract: The present invention aims at providing a semiconductor device capable of reliably preventing a wire bonded to an island from being disconnected due to a thermal shock, a temperature cycle and the like in mounting and capable of preventing remarkable increase in the process time. In the semiconductor device according to the present invention, a semiconductor chip is die-bonded to the surface of an island, one end of a first wire is wire-bonded to an electrode formed on the surface of the semiconductor chip to form a first bonding section and the other end of the first wire is wire-bonded to the island to form a second bonding section, while the semiconductor device is resin-sealed. A double bonding section formed by wire-bonding a second wire is provided on the second bonding section of the first wire wire-bonded onto the island.
    Type: Application
    Filed: April 14, 2006
    Publication date: January 7, 2010
    Applicant: ROHM CO., LTD.
    Inventors: Hideki Hiromoto, Sadamasa Fujii, Tsunemori Yamaguchi
  • Patent number: 7638860
    Abstract: A semiconductor device which can surely prevent a wire bonded to an island from breaking due to, for instance, thermal shock and temperature cycle upon mounting. The semiconductor device includes a semiconductor chip; an island die bonded with the semiconductor chip on the surface; and a wire for electrically connecting the electrode formed on the surface of the semiconductor chip with the island. The semiconductor device is further characterized in that the island has a die bonding region where the semiconductor chip is die bonded, a wire bonding region where the wire is wire bonded, and a continuous groove reaching a circumference of the island are formed between the die bonding region and the wire bonding region of the island.
    Type: Grant
    Filed: April 12, 2006
    Date of Patent: December 29, 2009
    Assignee: Rohm Co., Ltd.
    Inventors: Hideki Hiromoto, Sadamasa Fujii, Tsunemori Yamaguchi
  • Publication number: 20090289342
    Abstract: In an inventive semiconductor device production method, a one-side metal layer is first formed in a region located across a predetermined section line on one surface of a substrate. Further, an other-side metal layer is formed on the other surface of the substrate in a position opposed to the one-side metal layer. In turn, a continuous through-hole extending continuously through the other-side metal layer and the substrate is formed in a position located across the section line. Thereafter, a metal plating layer is formed on a surface of the other-side metal layer, an inner surface of the continuous through-hole and a portion of the one-side metal layer exposed to the continuous through-hole. Before the resulting substrate is cut into separate support boards, a portion of the other-side metal layer present on the section line and a portion of the metal plating layer present on this other-side metal layer portion are removed.
    Type: Application
    Filed: April 12, 2006
    Publication date: November 26, 2009
    Applicant: ROHM CO., LTD
    Inventors: Yasumasa Kasuya, Sadamasa Fujii
  • Patent number: 7612456
    Abstract: An inventive electronic device includes a substrate, a bump of a first metal material provided on a surface of the substrate, a bonding film of a second metal material provided on a top surface of the bump for bonding the electronic device to an electrical connection portion of a second device, the second metal material having a lower melting point in an elemental state than an alloy of the first metal material and the second metal material, and a diffusion prevention film of a third metal material provided between the top surface of the bump and the bonding film as covering at least part of the top surface of the bump, the third metal material having a lower diffusion coefficient than the second metal material with respect to the first metal material.
    Type: Grant
    Filed: June 16, 2005
    Date of Patent: November 3, 2009
    Assignee: Rohm Co., Ltd.
    Inventors: Sadamasa Fujii, Taro Nishioka
  • Publication number: 20090115050
    Abstract: An interposer and a semiconductor device including the interposer are provided, which can prevent thermal warpage of an insulative substrate thereof. The interposer is to be provided together with a semiconductor chip in a semiconductor device and, when the semiconductor device is mounted on a mount board, disposed between the semiconductor chip and the mount board. The interposer includes: an insulative substrate of an insulative resin; an island provided on one surface of the insulative substrate to be bonded to a rear surface of the semiconductor chip via a bonding agent; a thermal pad provided on the other surface of the insulative substrate opposite from the one surface in generally opposed relation to the island with the intervention of the insulative substrate; and a thermal via extending through the insulative substrate from the one surface to the other surface to connect the island to the thermal pad in a thermally conductive manner.
    Type: Application
    Filed: June 2, 2006
    Publication date: May 7, 2009
    Applicant: ROHM CO., LTD.
    Inventors: Yasumasa Kasuya, Sadamasa Fujii, Motoharu Haga
  • Publication number: 20090032919
    Abstract: A semiconductor device which can surely prevent a wire bonded to an island from breaking due to, for instance, thermal shock and temperature cycle upon mounting. The semiconductor device includes a semiconductor chip; an island die bonded with the semiconductor chip on the surface; and a wire for electrically connecting the electrode formed on the surface of the semiconductor chip with the island. The semiconductor device is further characterized in that the island has a die bonding region where the semiconductor chip is die bonded, a wire bonding region where the wire is wire bonded, and a continuous groove reaching a circumference of the island are formed between the die bonding region and the wire bonding region of the island.
    Type: Application
    Filed: April 12, 2006
    Publication date: February 5, 2009
    Inventors: Hideki Hiromoto, Sadamasa Fujii, Tsunemori Yamaguchi
  • Publication number: 20070075422
    Abstract: Disclosed is an electronic device comprising a substrate, a bump formed on a substrate surface and composed of a first metal material, a junction film for connection with an electrical connecting portion of another device which is formed on the top face of the bump and composed of a second metal material, the melting point of which second metal material itself is lower than the melting point of an alloy thereof with the first metal material, and a diffusion-preventing film which is so arranged between the top face of the bump and the junction film as to cover at least a part of the top face of the bump and composed of a third metal material whose diffusion coefficient in the first metal material is lower than that of the second metal material.
    Type: Application
    Filed: June 16, 2005
    Publication date: April 5, 2007
    Inventors: Sadamasa Fujii, Taro Nishioka