Patents by Inventor Sadanand Vinayak Deshpande

Sadanand Vinayak Deshpande has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Gate linewidth tailoring and critical dimension control for sub-100 nm devices using plasma etching
    Patent number: 6864041
    Abstract: A method of fabricating an electronic chip on a wafer in which a first mask at a predetermined lower resolution is developed on the wafer and then etched under a first set of conditions for a predetermined period to achieve a mask that is below the resolution limit of current lithography. The etched mask is then used as a hard mask for etching material on a lower layer.
    Type: Grant
    Filed: May 2, 2001
    Date of Patent: March 8, 2005
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey J. Brown, Sadanand Vinayak Deshpande, David V. Horak, Maheswaran Surendra, Len Y. Tsou, Qingyun Yang, Chienfan Yu, Ying Zhang
  • Gate linewidth tailoring and critical dimension control for sub-100 nm devices using plasma etching
    Publication number: 20020164546
    Abstract: A method of fabricating an electronic chip on a wafer in which a first mask at a predetermined lower resolution is developed on the wafer and then etched under a first set of conditions for a predetermined period to achieve a mask that is below the resolution limit of current lithography. The etched mask is then used as a hard mask for etching material on a lower layer.
    Type: Application
    Filed: May 2, 2001
    Publication date: November 7, 2002
    Applicant: International Business Machines Corporation
    Inventors: Jeffrey J. Brown, Sadanand Vinayak Deshpande, David V. Horak, Maheswaran Surendra, Len Y. Tsou, Qingyun Yang, Chienfan Yu, Ying Zhang