Patents by Inventor Sadao Imada

Sadao Imada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180061822
    Abstract: According to one embodiment, a semiconductor integrated circuit includes: a protection circuit including a first diode whose cathode is connected to a first wiring having a power-supply voltage and whose anode is connected to a first node, and a second diode whose anode is connected to a second wiring having a reference voltage and whose cathode is connected to the first node; a protection resistor that is connected to the first node at one end thereof and is connected to a second node at the other end thereof; a buffer circuit that is connected between the first wiring and the second wiring and has an input terminal to which a voltage at the second node is input; and a switching element that is connected between the first wiring and the second node.
    Type: Application
    Filed: February 26, 2017
    Publication date: March 1, 2018
    Inventors: Yoshimasa KANDA, Sadao IMADA
  • Patent number: 4962320
    Abstract: An input protection circuit for MOS devices includes a first resistor and a first parasitic bipolar transistor connected between an input pad and an input buffer circuit of a MOS device. The input protection circuit for MOS devices further includes a second resistor and a second parasitic bipolar transistor connected at a preceding stage of the input buffer circuit so that the gate oxide film of the input buffer circuit can be protected from being damaged by static charges or a voltage which is accidentally generated, without increasing the pattern size of the first parasitic bipolar transistor.
    Type: Grant
    Filed: July 13, 1989
    Date of Patent: October 9, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshio Okada, Sadao Imada, Mitsuru Shimizu