Patents by Inventor Sadao Miyazaki
Sadao Miyazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9921779Abstract: A memory apparatus, includes: a memory including memory regions; a table storing a memory address and a number of reading times of data; a first buffer storing first data from another memory apparatus and a first memory address of the first data; a second buffer storing second data to the another memory apparatus and a second memory address of the second data; and a controller configured to store, when a first number of reading times being minimum in the table is smaller than a second number of reading times of the first data, the first data and the first memory address into the first buffer and outputs third data in a memory region of the first number and a third memory address of the third data to the another memory apparatus via the second buffer, and rewrites the third data and memory address with the first data and memory address.Type: GrantFiled: April 25, 2016Date of Patent: March 20, 2018Assignee: FUJITSU LIMITEDInventors: Yoshitsugu Goto, Osamu Ishibashi, Sadao Miyazaki, Jin Abe, Masaru Itoh
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Patent number: 9542285Abstract: A memory device includes a storage unit in which a plurality of semiconductor chips each comprising a plurality of memory blocks respectively arranged in a planar direction and a plurality of redundant blocks respectively arranged in a planar direction are stacked, a detecting unit configured to detect a defect of each of the memory blocks in the storage unit; a checking unit configured to check free capacity in each of the redundant blocks in the storage unit, and a determining unit configured to determine a substitute block to be substituted for the memory block in which the defect has been detected from the redundant blocks having the free capacity.Type: GrantFiled: December 18, 2014Date of Patent: January 10, 2017Assignee: FUJITSU LIMITEDInventors: Sadao Miyazaki, Osamu Ishibashi, Jin Abe
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Publication number: 20160335029Abstract: A memory apparatus, includes: a memory including memory regions; a table storing a memory address and a number of reading times of data; a first buffer storing first data from another memory apparatus and a first memory address of the first data; a second buffer storing second data to the another memory apparatus and a second memory address of the second data; and a controller configured to store, when a first number of reading times being minimum in the table is smaller than a second number of reading times of the first data, the first data and the first memory address into the first buffer and outputs third data in a memory region of the first number and a third memory address of the third data to the another memory apparatus via the second buffer, and rewrites the third data and memory address with the first data and memory address.Type: ApplicationFiled: April 25, 2016Publication date: November 17, 2016Applicant: FUJITSU LIMITEDInventors: Yoshitsugu Goto, Osamu Ishibashi, Sadao Miyazaki, Jin Abe, Masaru ITOH
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Publication number: 20150355706Abstract: An electronic device includes: a nonvolatile memory; a volatile memory stacked over the nonvolatile memory; and a controller configured to store setting information of the volatile memory in the nonvolatile memory before cutting off power supply to the volatile memory, and to set the setting information stored in the nonvolatile memory to the volatile memory after resuming power supply to the volatile memory.Type: ApplicationFiled: April 27, 2015Publication date: December 10, 2015Applicant: FUJITSU LIMITEDInventors: Sadao MIYAZAKI, Osamu ISHIBASHI, Jin ABE, Yoshitsugu GOTO
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Patent number: 9099198Abstract: A semiconductor memory apparatus includes a memory block to include memory cells to hold data; a precharge control unit to control precharging the memory cells; a row decoder to output a row selection signal identifying a row address of the memory cells; an integral circuit to integrate a signal level of the row selection signal for a same row address, and to have an integral characteristic where an integral value of the signal level becomes a predetermined value when the row selection signal for the same row address is consecutively output for a predetermined number of times; and a determination unit to determine whether the integral value of the integral circuit becomes the predetermined value or greater. The precharge control unit turns off precharging the memory cells when the integral value of the integral circuit becomes the predetermined value or greater.Type: GrantFiled: November 14, 2014Date of Patent: August 4, 2015Assignee: FUJITSU LIMITEDInventors: Jin Abe, Osamu Ishibashi, Sadao Miyazaki
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Publication number: 20150199246Abstract: A memory device includes a storage unit in which a plurality of semiconductor chips each comprising a plurality of memory blocks respectively arranged in a planar direction and a plurality of redundant blocks respectively arranged in a planar direction are stacked, a detecting unit configured to detect a defect of each of the memory blocks in the storage unit; a checking unit configured to check free capacity in each of the redundant blocks in the storage unit, and a determining unit configured to determine a substitute block to be substituted for the memory block in which the defect has been detected from the redundant blocks having the free capacity.Type: ApplicationFiled: December 18, 2014Publication date: July 16, 2015Inventors: Sadao Miyazaki, Osamu Ishibashi, Jin Abe
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Publication number: 20150155027Abstract: A semiconductor memory apparatus includes a memory block to include memory cells to hold data; a precharge control unit to control precharging the memory cells; a row decoder to output a row selection signal identifying a row address of the memory cells; an integral circuit to integrate a signal level of the row selection signal for a same row address, and to have an integral characteristic where an integral value of the signal level becomes a predetermined value when the row selection signal for the same row address is consecutively output for a predetermined number of times; and a determination unit to determine whether the integral value of the integral circuit becomes the predetermined value or greater. The precharge control unit turns off precharging the memory cells when the integral value of the integral circuit becomes the predetermined value or greater.Type: ApplicationFiled: November 14, 2014Publication date: June 4, 2015Inventors: Jin Abe, Osamu Ishibashi, Sadao Miyazaki
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Patent number: 8972822Abstract: A memory module includes a plurality of memory chips stacked on top of one another, each of the plurality of memory chips including a memory cell unit that is divided into a plurality of blocks, and an address scrambling circuit that processes an input address signal and that selects a block to be operated.Type: GrantFiled: November 13, 2012Date of Patent: March 3, 2015Assignee: Fujitsu LimitedInventors: Rikizo Nakano, Osamu Ishibashi, Sadao Miyazaki
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Patent number: 8868990Abstract: A semiconductor memory device is disclosed that includes an ODT circuit configured to be connected to a bus which transmits a data signal or a data strobe signal between a memory block and an input-output terminal; a first switch configured to be inserted into the bus between the memory block and the ODT circuit; a mode controller configured to switch off the first switch during a test of the memory block; and an oscillator configured to be connected to the ODT circuit, wherein a test signal is supplied to the ODT circuit from the oscillator during the test of the memory block.Type: GrantFiled: March 27, 2012Date of Patent: October 21, 2014Assignee: Fujitsu LimitedInventors: Rikizo Nakano, Osamu Ishibashi, Sadao Miyazaki
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Patent number: 8738976Abstract: A memory error detecting apparatus for detecting an error of a subject memory, the memory error detecting apparatus includes a memory bus connected to the subject memory, a mirror memory connected to the memory bus so as to receive the same data as data to be written into and read from the subject memory, the received data being written into the mirror memory, an address acquiring portion configured to acquire an address related to the data written into the subject memory, a mirror memory controller configured to control data writing or reading to or from the mirror memory on the basis of the acquired address, a comparator configured to compare data read from the subject memory and data read from the mirror memory, and an error detector configured to detect a data error on the basis of a result of the comparison.Type: GrantFiled: June 17, 2011Date of Patent: May 27, 2014Assignee: Fujitsu LimitedInventors: Rikizo Nakano, Osamu Ishibashi, Sadao Miyazaki
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Patent number: 8495463Abstract: A memory control device is provided. The memory control device is configured to control access to a storage device including a plurality of storage areas. The memory control device includes a defect detecting unit configured to detect a defective area of a storage area into which data may not be stored. The memory control device also includes a storage processing unit configured to store defect information including address information of the defective area detected using the defect detecting unit into a memory area. A data writing unit is also included in the memory control device. The data writing unit is configured to write data, which has been written into the defective area, into a storage area other than the storage area comprising the defective area based on the defect information stored using the storage processing unit.Type: GrantFiled: March 17, 2010Date of Patent: July 23, 2013Assignee: Fujitsu LimitedInventors: Sadao Miyazaki, Osamu Ishibashi, Rikizo Nakano
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Patent number: 8473675Abstract: A memory system includes a first memory that is used as a main memory of a target device, a second memory that has an access speed lower than that of the first memory, a securing section that secures a predetermined area of the first memory as a temporary storage area of the second memory, and a memory control section that receives an instruction to write data into the second memory, temporarily stores the data into the first memory and also transfers the stored data from the first memory to the second memory.Type: GrantFiled: July 12, 2010Date of Patent: June 25, 2013Assignee: Fujitsu LimitedInventors: Sadao Miyazaki, Osamu Ishibashi, Rikizo Nakano
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Patent number: 8423842Abstract: A test apparatus for testing a memory device including a memory cell. The test apparatus includes a storage and a controller. The storage stores a first value. The controller executes, at a given timing, determining a second value which is a threshold limit value to read data of the memory cell correctly on the basis of an output of the memory cell, calculating a difference between the first value and the second value, outputting a deterioration information on the basis of the difference between the first value and the second value, and updating the first value stored in the storage to the second value.Type: GrantFiled: May 18, 2010Date of Patent: April 16, 2013Assignee: Fujitsu LimitedInventors: Rikizo Nakano, Osamu Ishibashi, Sadao Miyazaki
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Publication number: 20120254663Abstract: A semiconductor memory device is disclosed that includes an ODT circuit configured to be connected to a bus which transmits a data signal or a data strobe signal between a memory block and an input-output terminal; a first switch configured to be inserted into the bus between the memory block and the ODT circuit; a mode controller configured to switch off the first switch during a test of the memory block; and an oscillator configured to be connected to the ODT circuit, wherein a test signal is supplied to the ODT circuit from the oscillator during the test of the memory block.Type: ApplicationFiled: March 27, 2012Publication date: October 4, 2012Applicant: FUJITSU LIMITEDInventors: Rikizo Nakano, Osamu Ishibashi, Sadao Miyazaki
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Patent number: 8135971Abstract: A data processing apparatus includes a CPU including a register, a cache memory, a main memory configured to exchange data with the cache memory, a control part configured to control the exchanging of data between the main memory and the cache memory, and a power supply part configured to supply power to the register, the cache memory, and the main memory. The register, the cache memory, and the main memory are each configured to store data and maintain the stored data therein without being supplied with the power from the power supply part. The control part is configured to stop the CPU from accessing the register, the cache memory, and the main memory where an abnormality occurs in the power supply part.Type: GrantFiled: July 1, 2009Date of Patent: March 13, 2012Assignee: Fujitsu LimitedInventors: Sadao Miyazaki, Osamu Ishibashi, Rikizo Nakano, Yoshinori Mesaki
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Publication number: 20110314347Abstract: A memory error detecting apparatus for detecting an error of a subject memory, the memory error detecting apparatus includes a memory bus connected to the subject memory, a mirror memory connected to the memory bus so as to receive the same data as data to be written into and read from the subject memory, the received data being written into the mirror memory, an address acquiring portion configured to acquire an address related to the data written into the subject memory, a mirror memory controller configured to control data writing or reading to or from the mirror memory on the basis of the acquired address, a comparator configured to compare data read from the subject memory and data read from the mirror memory, and an error detector configured to detect a data error on the basis of a result of the comparison.Type: ApplicationFiled: June 17, 2011Publication date: December 22, 2011Applicant: FUJITSU LIMITEDInventors: Rikizo NAKANO, Osamu ISHIBASHI, Sadao MIYAZAKI
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Publication number: 20110010508Abstract: A memory system includes a first memory that is used as a main memory of a target device, a second memory that has an access speed lower than that of the first memory, a securing section that secures a predetermined area of the first memory as a temporary storage area of the second memory, and a memory control section that receives an instruction to write data into the second memory, temporarily stores the data into the first memory and also transfers the stored data from the first memory to the second memory.Type: ApplicationFiled: July 12, 2010Publication date: January 13, 2011Applicant: FUJITSU LIMITEDInventors: Sadao Miyazaki, Osamu Ishibashi, Rikizo Nakano
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Publication number: 20100313086Abstract: A test apparatus is for testing a memory device including a memory cell. The test apparatus includes a storage and a controller. The storage stores a first value. The controller executes, at a given timing, determining a second value which is a threshold limit value to read data of the memory cell correctly on the basis of an output of the memory cell, calculating a difference between the first value and the second value, outputting a deterioration information on the basis of the difference between the first value and the second value, and updating the first value stored in the storage to the second value.Type: ApplicationFiled: May 18, 2010Publication date: December 9, 2010Applicant: FUJITSU LIMITEDInventors: Rikizo Nakano, Osamu Ishibashi, Sadao Miyazaki
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Publication number: 20100251041Abstract: A memory control device is provided. The memory control device is configured to control access to a storage device including a plurality of storage areas. The memory control device includes a defect detecting unit configured to detect a defective area of a storage area into which data may not be stored. The memory control device also includes a storage processing unit configured to store defect information including address information of the defective area detected using the defect detecting unit into a memory area. A data writing unit is also included in the memory control device. The data writing unit is configured to write data, which has been written into the defective area, into a storage area other than the storage area comprising the defective area based on the defect information stored using the storage processing unit.Type: ApplicationFiled: March 17, 2010Publication date: September 30, 2010Applicant: FUJITSU LIMITEDInventors: Sadao MIYAZAKI, Osamu ISHIBASHI, Rikizo NAKANO
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Publication number: 20100058094Abstract: A data processing apparatus includes a CPU including a register, a cache memory, a main memory configured to exchange data with the cache memory, a control part configured to control the exchanging of data between the main memory and the cache memory, and a power supply part configured to supply power to the register, the cache memory, and the main memory. The register, the cache memory, and the main memory are each configured to store data and maintain the stored data therein without being supplied with the power from the power supply part. The control part is configured to stop the CPU from accessing the register, the cache memory, and the main memory where an abnormality occurs in the power supply part.Type: ApplicationFiled: July 1, 2009Publication date: March 4, 2010Applicant: FUJITSU LIMITEDInventors: Sadao Miyazaki, Osamu Ishibashi, Rikizo Nakano, Yoshinori Mesaki