Patents by Inventor Sadao Nakayama
Sadao Nakayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9373593Abstract: A method of manufacturing a semiconductor device, includes providing a multi-chip interconnection substrate having an upper surface and a lower surface, providing a semiconductor chip having a main surface and a back surface, making the back surface of the semiconductor chip and the upper surface of the multi-chip interconnection substrate face each other and mounting the semiconductor chips in the chip mounting areas of the multi-chip interconnection substrate through a bonding adhesive, coupling the electrode pads formed on the main surface of each of the semiconductor chips with the bonding pads formed on the upper surface of the multi-chip interconnection substrate by the conductive wires respectively, forming a resin sealing body by resin-sealing the semiconductor chips, the conductive wires, and the upper surface of the multi-chip interconnection substrate, and forming a plurality of solder balls to be coupled to a plurality of bump lands formed on the lower surface of the multi-chip interconnection subType: GrantFiled: June 8, 2015Date of Patent: June 21, 2016Assignee: Renesas Electronics CorporationInventors: Sadao Nakayama, Yoshihiro Matsuura
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Patent number: 9159681Abstract: A semiconductor device which uses a semiconductor chip originally designed for flip chip bonding and is assembled by a wire bonding process to reduce the cost of assembling a semiconductor product. A second electrode pad group and a fourth electrode pad group are located in the central area of the semiconductor chip and a first electrode pad group and a third electrode pad group are located adjacently to the two long sides of the semiconductor chip. The electrode pads of each electrode group are electrically coupled with a plurality of conductive wires. The layouts of the wiring layers formed in an interconnection substrate are modified so that the wire-bonded semiconductor device is the same as a flip-chip-bonded semiconductor device in terms of the positions of input/output signals.Type: GrantFiled: July 23, 2013Date of Patent: October 13, 2015Assignee: Renesas Electronics CorporationInventors: Sadao Nakayama, Yoshihiro Matsuura
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Publication number: 20150270244Abstract: A method of manufacturing a semiconductor device, includes providing a multi-chip interconnection substrate having an upper surface and a lower surface, providing a semiconductor chip having a main surface and a back surface, making the back surface of the semiconductor chip and the upper surface of the multi-chip interconnection substrate face each other and mounting the semiconductor chips in the chip mounting areas of the multi-chip interconnection substrate through a bonding adhesive, coupling the electrode pads formed on the main surface of each of the semiconductor chips with the bonding pads formed on the upper surface of the multi-chip interconnection substrate by the conductive wires respectively, forming a resin sealing body by resin-sealing the semiconductor chips, the conductive wires, and the upper surface of the multi-chip interconnection substrate, and forming a plurality of solder balls to be coupled to a plurality of bump lands formed on the lower surface of the multi-chip interconnection subType: ApplicationFiled: June 8, 2015Publication date: September 24, 2015Inventors: Sadao NAKAYAMA, Yoshihiro MATSUURA
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Publication number: 20140027919Abstract: A semiconductor device which uses a semiconductor chip originally designed for flip chip bonding and is assembled by a wire bonding process to reduce the cost of assembling a semiconductor product. A second electrode pad group and a fourth electrode pad group are located in the central area of the semiconductor chip and a first electrode pad group and a third electrode pad group are located adjacently to the two long sides of the semiconductor chip. The electrode pads of each electrode group are electrically coupled with a plurality of conductive wires. The layouts of the wiring layers formed in an interconnection substrate are modified so that the wire-bonded semiconductor device is the same as a flip-chip-bonded semiconductor device in terms of the positions of input/output signals.Type: ApplicationFiled: July 23, 2013Publication date: January 30, 2014Applicant: Renesas Electronics CorporationInventors: Sadao Nakayama, Yoshihiro Matsuura
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Patent number: 7066131Abstract: In the present invention, there is provided a cylinder head in which seat rings, against which are placed intake valves, are mounted respectively on a plurality of intake ports that communicate with a combustion chamber of an internal combustion engine, and, among the plurality of intake ports, an intake port on which is mounted an eccentric seat ring, with a center of an inner diameter of this eccentric seat ring being eccentric relative to a center of an outer diameter of this eccentric seat ring, is present together with an intake port on which is mounted a standard seat ring, with a center of an inner diameter of this standard seat ring matching a center of an outer diameter of this standard seat ring. As a result, a flow coefficient can be secured using the intake port on which the standard seat ring is mounted, and the swirl flow can be strengthened using the intake port on which the eccentric seat ring is mounted.Type: GrantFiled: February 13, 2002Date of Patent: June 27, 2006Assignee: Niigata Power Systems Co., Ltd.Inventors: Satoru Goto, Sadao Nakayama, Yoshiharu Ono
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Patent number: 7066164Abstract: The present invention has been realized in order to keep the cylinder exhaust temperature of a gas engine within a predetermined range, and thereby prevent the generation of misfire and knocking. In the present invention, in S1, when the number of rotations of the engine is greater than a predetermined number, in S2, the exhaust temperatures of the cylinders are sampled at predetermined intervals, in S3, an average of the exhaust temperatures is calculated, in S4, the load factor at that point is determined, in S5, the average exhaust temperature Tave is compared with the exhaust temperature T(n) of each cylinder, and it is determined whether the deviation ?Tn is greater or smaller than the set deviation Tlimit for that load factor. When the deviation ?Tn is smaller, the exhaust temperature is within the set deviation and there is no need to adjust the fuel spray period, and therefore the sequence returns to S2.Type: GrantFiled: August 29, 2002Date of Patent: June 27, 2006Assignee: Niigata Power Systems Co., Ltd.Inventors: Yoshiharu Ono, Satoru Goto, Yoshifumi Nishi, Sadao Nakayama
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Patent number: 6958532Abstract: A semiconductor storage device enables various plural memories to be mounted on the same package, and even though size of respective chips and/or position of bonding pad are different, it is capable of providing a stack MCP in which the chips are superimposed. It causes wiring sheet to intervene between an upper chip and a lower chip. There are provided bonding pads and a wiring pattern for connecting these bonding pads in the wiring sheet. A bonding pad of the upper chip is connected to the bonding pad by a first bonding wire, while the bonding pad is connected to a bonding pad of the package substrate by a second bonding wire. According to this construction, the signal from the upper chip is transmitted to the package substrate via the wiring sheet.Type: GrantFiled: June 14, 2000Date of Patent: October 25, 2005Assignee: NEC Electronics CorporationInventor: Sadao Nakayama
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Publication number: 20040084005Abstract: In the present invention, there is provided a cylinder head in which seat rings, against which are placed intake valves, are mounted respectively on a plurality of intake ports that communicate with a combustion chamber of an internal combustion engine, and, among the plurality of intake ports, an intake port on which is mounted an eccentric seat ring, with a center of an inner diameter of this eccentric seat ring being eccentric relative to a center of an outer diameter of this eccentric seat ring, is present together with an intake port on which is mounted a standard seat ring, with a center of an inner diameter of this standard seat ring matching a center of an outer diameter of this standard seat ring. As a result, a flow coefficient can be secured using the intake port on which the standard seat ring is mounted, and the swirl flow can be strengthened using the intake port on which the eccentric seat ring is mounted.Type: ApplicationFiled: October 9, 2003Publication date: May 6, 2004Inventors: Satoru Goto, Sadao Nakayama, Yoshiharu Ono
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Publication number: 20040003805Abstract: The present invention has been realized in order to keep the cylinder exhaust temperature of a gas engine within a predetermined range, and thereby prevent the generation of misfire and knocking. In the present invention, in S1, when the number of rotations of the engine is greater than a predetermined number, in S2, the exhaust temperatures of the cylinders are sampled at predetermined intervals, in S3, an average of the exhaust temperatures is calculated, in S4, the load factor at that point is determined, in S5, the average exhaust temperature Tave is compared with the exhaust temperature T(n) of each cylinder, and it is determined whether the deviation &Dgr;Tn is greater or smaller than the set deviation Tlimit for that load factor. When the deviation &Dgr;Tn is smaller, the exhaust temperature is within the set deviation and there is no need to adjust the fuel spray period, and therefore the sequence returns to S2.Type: ApplicationFiled: April 23, 2003Publication date: January 8, 2004Inventors: Yoshiharu Ono, Satoru Goto, Yoshifumi NIshi, Sadao Nakayama
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Patent number: 6472608Abstract: The present invention provides a semiconductor device of the BGA configuration comprising: a wiring layer 2 arranged on a circuit substrate 1 via an insulation layer; a land metal portion 2 formed on the wiring layer 2; a solder resist 4 layered so as to cover the land metal excluding a center portion thereof and the entire surface of the circuit substrate 1; and a solder ball 5 arranged on the land metal portion defined and surrounded by the solder resist 4; wherein the land metal portion 3 has a solder ball contact surface having a groove (or a line-shaped protrusion) 7 extending continuously.Type: GrantFiled: February 9, 2001Date of Patent: October 29, 2002Assignee: NEC CorporationInventor: Sadao Nakayama
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Publication number: 20010015285Abstract: The present invention provides a semiconductor device of the BGA configuration comprising: a wiring layer 2 arranged on a circuit substrate 1 via an insulation layer; a land metal portion 2 formed on the wiring layer 2; a solder resist 4 layered so as to cover the land metal excluding a center portion thereof and the entire surface of the circuit substrate 1; and a solder ball 5 arranged on the land metal portion defined and surrounded by the solder resist 4; wherein the land metal portion 3 has a solder ball contact surface having a groove (or a line-shaped protrusion) 7 extending continuously.Type: ApplicationFiled: February 9, 2001Publication date: August 23, 2001Inventor: Sadao Nakayama
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Patent number: 6209511Abstract: The present invention relates to a lean combustion gas engine which receives a drive output by means of supplying and combusting gas fuel in a main combustion chamber. The lean combustion engine of the present invention comprises: a main combustion chamber (1) which is surrounded by a piston (3), a cylinder (2) and a cylinder head (4); a precombustion chamber (30) equipped with a pilot fuel injection valve; and a spark plug (11) which serves as an ignition source for the fuel-air mixture within the main combustion chamber; wherein, the spark plug and pilot fuel injection valve-equipped precombustion chamber are provided in said cylinder head.Type: GrantFiled: May 10, 1999Date of Patent: April 3, 2001Assignee: Niigata Engineering Co., Ltd.Inventors: Satoru Goto, Yoshifumi Nishi, Sadao Nakayama, Takeyuki Sakagami
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Patent number: 5838626Abstract: A non-volatile memory includes a plurality of cell blocks, each including a plurality of non-volatile memory cells which are electrically rewritable. Each non-volatile memory cell has a source, a drain, a control gate and a floating gate. The non-volatile memory is further provided with a bias controller which can concurrently apply a first bias voltage to the source and a second bias voltage to the drain of each non-volatile memory cell In call blocks. Preferably, the bias controller applies the first bias voltage to both the source and the drain of each non-volatile memory cell.Type: GrantFiled: August 8, 1997Date of Patent: November 17, 1998Assignee: NEC CorporationInventor: Sadao Nakayama
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Patent number: 5808936Abstract: A nonvolatile memory includes a matrix array of nonvolatile memory cells arranged in rows and columns, ones of the memory cells arranged in rows being connected to word lines and ones of the memory cells arranged in columns being connected to bit lines. A selection logic circuitry receives programming data and produces a row selection signal and a column selection signal. A row decoder is responsive to the row selection signal for selecting one of the word lines, and a column decoder is responsive to the column selection signal for selecting at least one of the bit lines. When the nonvolatile memory is programmed, the programming data is supplied to the selection logic circuitry, and a write-in voltage is supplied to the row decoder for a period that is inversely variable with the write-in voltage so that hot electrons are trapped in the memory cell which is connected to the selected bit line as well as to the selected word line.Type: GrantFiled: November 25, 1996Date of Patent: September 15, 1998Assignee: NEC CorporationInventor: Sadao Nakayama