Patents by Inventor Sadar Ahmed
Sadar Ahmed has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10944421Abstract: The least-significant-bits (LSBs) of a first data word of a first subset of a first plurality of data words may be compared to the LSBs of each data word of a second subset of a second plurality of data words. The first data word may then be mapped to a second data word of the second subset. A number of LSBs of the second data word matching LSBs of the first data word may be greater than a respective number of LSBs of each data word of a third subset of the second subset matching the LSBs of the first data word, where the third subset excludes the second data word and a most-significant-bit (MSB) of the second data word may be the same as a MSB of the first data word.Type: GrantFiled: August 30, 2019Date of Patent: March 9, 2021Assignee: Oracle International CorporationInventor: Sadar Ahmed
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Publication number: 20190386678Abstract: The least-significant-bits (LSBs) of a first data word of a first subset of a first plurality of data words may be compared to the LSBs of each data word of a second subset of a second plurality of data words. The first data word may then be mapped to a second data word of the second subset. A number of LSBs of the second data word matching LSBs of the first data word may be greater than a respective number of LSBs of each data word of a third subset of the second subset matching the LSBs of the first data word, where the third subset excludes the second data word and a most-significant-bit (MSB) of the second data word may be the same as a MSB of the first data word.Type: ApplicationFiled: August 30, 2019Publication date: December 19, 2019Inventor: Sadar Ahmed
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Patent number: 10404273Abstract: The least-significant-bits (LSBs) of a first data word of a first subset of a first plurality of data words may be compared to the LSBs of each data word of a second subset of a second plurality of data words. The first data word may then be mapped to a second data word of the second subset. A number of LSBs of the second data word matching LSBs of the first data word may be greater than a respective number of LSBs of each data word of a third subset of the second subset matching the LSBs of the first data word, where the third subset excludes the second data word and a most-significant-bit (MSB) of the second data word may be the same as a MSB of the first data word.Type: GrantFiled: May 7, 2018Date of Patent: September 3, 2019Assignee: Oracle International CorporationInventor: Sadar Ahmed
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Publication number: 20180254782Abstract: The least-significant-bits (LSBs) of a first data word of a first subset of a first plurality of data words may be compared to the LSBs of each data word of a second subset of a second plurality of data words. The first data word may then be mapped to a second data word of the second subset. A number of LSBs of the second data word matching LSBs of the first data word may be greater than a respective number of LSBs of each data word of a third subset of the second subset matching the LSBs of the first data word, where the third subset excludes the second data word and a most-significant-bit (MSB) of the second data word may be the same as a MSB of the first data word.Type: ApplicationFiled: May 7, 2018Publication date: September 6, 2018Inventor: Sadar Ahmed
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Patent number: 9966970Abstract: A method for determining a mapping between two code spaces is disclosed. The method may include receiving first and second plurality of data words. The least-significant-bits (LSBs) of a first data word of a first subset of the first plurality of data words may be compared to the LSBs of each data word of a second subset of the second plurality of data words. The first data word may then be mapped to a second data word of the second subset. A number of LSBs of the second data word matching LSBs of the first data word may be greater than a respective number of LSBs of each data word of a third subset of the second subset matching the LSBs of the first data word, where the third subset excludes the second data word and a most-significant-bit (MSB) of the second data word may be the same as a MSB of the first data word.Type: GrantFiled: April 9, 2015Date of Patent: May 8, 2018Assignee: Oracle International CorporationInventor: Sadar Ahmed
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Patent number: 9484949Abstract: An apparatus and method for encoding data are disclosed that may allow for variable run length encoding of data to be transmitted. An ordered stream of data bits is received from a logic circuit, and N sequential data bits of the stream are selected, where N is a positive integer. Of the N sequential data bits, M sequential data bits are selected, wherein M is a positive integer less than N. The M sequential data bits are then encoded to generate a code word that includes P data bits, wherein P is a positive integer greater than M and less than N. The code word is then concatenated with a subset of the N sequential data bits that excludes the M sequential data bits to form a transmission word. A transmit unit then sends the data bits of the transmission word in a serial fashion.Type: GrantFiled: April 9, 2015Date of Patent: November 1, 2016Assignee: Oracle International CorporationInventors: Sadar Ahmed, Robert P. Masleid
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Publication number: 20160301426Abstract: A method for determining a mapping between two code spaces is disclosed. The method may include receiving first and second plurality of data words. The least-significant-bits (LSBs) of a first data word of a first subset of the first plurality of data words may be compared to the LSBs of each data word of a second subset of the second plurality of data words. The first data word may then be mapped to a second data word of the second subset. A number of LSBs of the second data word matching LSBs of the first data word may be greater than a respective number of LSBs of each data word of a third subset of the second subset matching the LSBs of the first data word, where the third subset excludes the second data word and a most-significant-bit (MSB) of the second data word may be the same as a MSB of the first data word.Type: ApplicationFiled: April 9, 2015Publication date: October 13, 2016Inventor: Sadar Ahmed
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Publication number: 20160301422Abstract: An apparatus and method for encoding data are disclosed that may allow for variable run length encoding of data to be transmitted. An ordered stream of data bits is received from a logic circuit, and N sequential data bits of the stream are selected, where N is a positive integer. Of the N sequential data bits, M sequential data bits are selected, wherein M is a positive integer less than N. The M sequential data bits are then encoded to generate a code word that includes P data bits, wherein P is a positive integer greater than M and less than N. The code word is then concatenated with a subset of the N sequential data bits that excludes the M sequential data bits to form a transmission word. A transmit unit then sends the data bits of the transmission word in a serial fashion.Type: ApplicationFiled: April 9, 2015Publication date: October 13, 2016Inventors: Sadar Ahmed, Robert P. Masleid
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Patent number: 8606840Abstract: A fused multiply add (FMA) unit includes an alignment counter configured to calculate an alignment shift count, an aligner configured to align an addend input based on the alignment shift count and output an aligned addend, a multiplier configured to multiply a first multiplicand input and a second multiplicand input and output a product, an adder configured to add the aligned addend and the product and output a sum without determining the sign of the sum or complementing the sum, a normalizer configured to receive the sum directly from the adder and normalize the sum irrespective of the sign of the sum and output a normalized sum, and a rounder configured to round and complement-adjust the normalized sum and output a final mantissa.Type: GrantFiled: March 17, 2010Date of Patent: December 10, 2013Assignee: Oracle International CorporationInventor: Sadar Ahmed
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Publication number: 20110231460Abstract: A fused multiply add (FMA) unit includes an alignment counter configured to calculate an alignment shift count, an aligner configured to align an addend input based on the alignment shift count and output an aligned addend, a multiplier configured to multiply a first multiplicand input and a second multiplicand input and output a product, an adder configured to add the aligned addend and the product and output a sum without determining the sign of the sum or complementing the sum, a normalizer configured to receive the sum directly from the adder and normalize the sum irrespective of the sign of the sum and output a normalized sum, and a rounder configured to round and complement-adjust the normalized sum and output a final mantissa.Type: ApplicationFiled: March 17, 2010Publication date: September 22, 2011Applicant: ORACLE INTERNATIONAL CORPORATIONInventor: Sadar Ahmed
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Patent number: 6990505Abstract: A floating point unit capable of converting a 64-bit integer number to a floating point format is provided. The floating point unit includes an 11-bit zero/one complement detect circuitry in an exponent datapath of the floating point unit, where the 11-bit zero/one complement detect circuitry is used to determine a shift count for a right shifter in a large exponent difference mantissa datapath of the floating point unit. The 11-bit zero/one complement detect circuitry determines shift counts based on particular bit groupings of the 64-bit operand.Type: GrantFiled: May 9, 2002Date of Patent: January 24, 2006Assignee: Sun Microsystems, Inc.Inventor: Sadar Ahmed
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Publication number: 20030212720Abstract: A floating point unit capable of converting a 64-bit integer number to a floating point format is provided. The floating point unit includes an 11-bit zero/one complement detect circuitry in an exponent datapath of the floating point unit, where the 11-bit zero/one complement detect circuitry is used to determine a shift count for a right shifter in a large exponent difference mantissa datapath of the floating point unit. The 11-bit zero/one complement detect circuitry determines shift counts based on particular bit groupings of the 64-bit operand.Type: ApplicationFiled: May 9, 2002Publication date: November 13, 2003Inventor: Sadar Ahmed