Patents by Inventor Sadarshan Kumar

Sadarshan Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6914848
    Abstract: A memory, such as a register file or a cache, having stack pMOSFETs shared among its word line drivers, where a stack pMOSFET shared by a set of word line drivers has its drain connected to the sources of the pMOSFETs in the set or word line drivers, and were each stack pMOSFET is controlled by an enable signal so as to turn ON only if its corresponding set of word line drivers is enabled. The enable signal may be provided by a write or read enable port, or by the memory's address decoder. The stacked configuration of pMOSFETs significantly reduces sub-threshold leakage current in the word line drivers with very little penalty in performance.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: July 5, 2005
    Assignee: Intel Corporation
    Inventors: Shahram Jamshidi, Sadarshan Kumar, Sadhana Madhyastha
  • Publication number: 20040252574
    Abstract: A memory, such as a register file or a cache, having stack pMOSFETs shared among its word line drivers, where a stack pMOSFET shared by a set of word line drivers has its drain connected to the sources of the pMOSFETs in the set or word line drivers, and were each stack pMOSFET is controlled by an enable signal so as to turn ON only if its corresponding set of word line drivers is enabled. The enable signal may be provided by a write or read enable port, or by the memory's address decoder. The stacked configuration of pMOSFETs significantly reduces sub-threshold leakage current in the word line drivers with very little penalty in performance.
    Type: Application
    Filed: June 12, 2003
    Publication date: December 16, 2004
    Inventors: Shahram Jamshidi, Sadarshan Kumar, Sadhana Madhyastha