Patents by Inventor Sadashiva Rao

Sadashiva Rao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Column defect detection in a content addressable memory
    Patent number: 7277307
    Abstract: A content addressable memory (CAM) device. For one embodiment, the CAM device includes a CAM array having a plurality of columns of CAM cells, a plurality of storage elements, each for storing a column pass/fail signal indicating whether a corresponding column of CAM cells is designated as good or as bad, and a test circuit having an output coupled to the storage elements, and configured to generate the column pass/fail signals during a column test sequence.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: October 2, 2007
    Assignee: NetLogic Microsystems, Inc.
    Inventor: Sadashiva Rao Yelluru
  • Efficient back bias (VBB) detection and control scheme for low voltage drams
    Patent number: 6205061
    Abstract: An efficient back bias (VBB) detection and control circuit make possible a low voltage memory device and includes an on-chip VBB level sensor (38) that includes a dynamic voltage reference shift circuit (40, 42, 44, 46) for establishing a first voltage level (−(|2VTP|+VTN)) during power-up and a second voltage level (−|2VTP| during normal operation. The first voltage level is of a deeper level for achieving a short power-up interval. The second voltage level has a level less deep than said first voltage for achieving low power operation.
    Type: Grant
    Filed: November 10, 1999
    Date of Patent: March 20, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Vipul Surlekar, Sadashiva Rao
  • Efficient back bias (V.sub.BB) detection and control scheme for low voltage DRAMS
    Patent number: 6115295
    Abstract: An efficient back bias (V.sub.BB) detection and control circuit make possible a low voltage memory device and includes an on-chip V.sub.BB level sensor (38) that includes a dynamic voltage reference shift circuit (40, 42, 44, 46) for establishing a first voltage level (-(.vertline.2 VTP.vertline.+VTN)) during power-up and a second voltage level (-.vertline.2 VTP.vertline. during normal operation. The first voltage level is of a deeper level for achieving a short power-up interval. The second voltage level has a level less deep than said first voltage for achieving low power operation.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: September 5, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Vipul Surlekar, Sadashiva Rao
  • System for improved response time output buffer unit having individual stages for signal generation and buffering and output stage applying signal determined by input signal
    Patent number: 5831450
    Abstract: An output buffer unit for use with a dynamic random access memory includes a first stage for generating complementary logic signals. In an intermediate stage, separate from the generation of the complementary signals, the complementary signals are buffered for application to the output driver stages. By separation of the signal generation stages from the buffering stages, the speed of the logic level-to-logic level transitions can be increased.
    Type: Grant
    Filed: May 31, 1996
    Date of Patent: November 3, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Biju Velayudhan, Sadashiva Rao