Patents by Inventor Sadayoshi Handa

Sadayoshi Handa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160323092
    Abstract: A transfer apparatus comprising a first switch configured to generate a first timing pulse based on a reference clock, transmit first information related to the first timing pulse, a second switch configured to, generate a second timing pulse based on the reference clock, transmit second information related to the second timing pulse, a line interface configured to receive signal data and store the signal data in a memory, transfer the signal data based on the first timing pulse when the first information is received, and transfer the signal data based on the information when the first information is not received and the second information is received, detect a phase shift between the first timing pulse and the second timing pulse, transmit the phase shift to the second switch, wherein the second switch is configured to correct, based on the phase shift, a timing that the second timing pulse is generated.
    Type: Application
    Filed: March 18, 2016
    Publication date: November 3, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Sadayoshi HANDA, Takanori Yasui, Hirofumi Fujiyama, Hiroshi KUNITAKE, Mitsuhiro KAWAGUCHI
  • Patent number: 7496330
    Abstract: In a phase adjusting method and device in which a phase deviation between main signal frames themselves returned from a station end device through an antenna end device to the station end device without using a control signal for the phase adjustment, a reference signal generated in a first device is commonly mapped to respective down main signal frames of a first and a second system to be outputted to a second device, the second device maps, pointer values indicating timings of the reference signal in the respective down main signal frames to respective up main signal frames of the first and the second system to be outputted to the first device, and the first device extracts respective pointer values from the respective main signal frames and adjust frames of the respective up main signal frames based on the respective pointer values.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: February 24, 2009
    Assignee: Fujitsu Limited
    Inventors: Yoshimi Toyoda, Hironobu Sunden, Sadayoshi Handa, Isshin Fujii, Osamu Kaise
  • Publication number: 20090003205
    Abstract: A method for a load distribution control of packet transmission includes calculating bandwidths of individual physical ports at a time when inputted packets are distributed to the plurality of physical ports, using each of a plurality of hash calculation formulas; selecting one of the hash calculation formulas so that the calculated bandwidths of the packets for the respective physical ports may become uniform; and distributing and delivering the packets to the respective physical ports using the updated hash calculation formula.
    Type: Application
    Filed: June 23, 2008
    Publication date: January 1, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Satoshi Tomie, Hideki Shiono, Masaki Hiromori, Takanori Yasui, Sadayoshi Handa, Hirohumi Fujiyama
  • Publication number: 20080077741
    Abstract: A dynamic memory management method and apparatus wherein an area of a memory is partitioned into a plurality of areas to form memory banks. The different priority classes share the memory banks. A policer (write controller) dynamically assigns input frame data of a plurality of classes having different degrees of priority to memory banks in accordance with the degrees of priority and stores the data there for each priority class. A scheduler (read controller) sequentially reads out the data from the frame data stored in the memory bank assigned to the class having the highest degree of priority and transmits the same. For storage of frame data of a priority of class input in a burst like manner, a plurality of memory banks are assigned to that priority class so as to raise the burst tolerance. By controlling writing and reading of data in units of memory banks, the control can be simplified. Due to this, the efficiency of usage of memory is improved and the write/read control is simplified.
    Type: Application
    Filed: July 30, 2007
    Publication date: March 27, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Takanori Yasui, Hideki Shiono, Masaki Hiromori, Hirofumi Fujiyama, Satoshi Tomie, Yasuhiro Yamauchi, Sadayoshi Handa
  • Publication number: 20060105728
    Abstract: In a phase adjusting method and device in which a phase deviation between main signal frames themselves returned from a station end device through an antenna end device to the station end device without using a control signal for the phase adjustment, a reference signal generated in a first device is commonly mapped to respective down main signal frames of a first and a second system to be outputted to a second device, the second device maps, pointer values indicating timings of the reference signal in the respective down main signal frames to respective up main signal frames of the first and the second system to be outputted to the first device, and the first device extracts respective pointer values from the respective main signal frames and adjust frames of the respective up main signal frames based on the respective pointer values.
    Type: Application
    Filed: February 28, 2005
    Publication date: May 18, 2006
    Inventors: Yoshimi Toyoda, Hironobu Sunden, Sadayoshi Handa, Isshin Fujii, Osamu Kaise