Patents by Inventor Sadayoshi Yoshida

Sadayoshi Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5854577
    Abstract: A variable frequency microwave oscillator comprises an oscillation FET of a junction type, a fixed impedance block connected to the source of the oscillation FET for determining the drain impedance on the source of the oscillation FET, and a variable bias block including inductance connected to the drain of the oscillation FET and an impedance controlling junction FET both for determining the drain impedance of the oscillation FET of a junction type. The gate of the oscillation FET is connected to an external resonance block which generates an oscillation in association with the negative impedance appearing on the gate of the oscillation FET. The oscillation frequency is controlled by a control voltage applied to the gate of the impedance controlling FET.
    Type: Grant
    Filed: April 30, 1997
    Date of Patent: December 29, 1998
    Assignee: NEC Corporation
    Inventors: Sadayoshi Yoshida, Kazunari Sato
  • Patent number: 5341111
    Abstract: A microwave oscillator circuit is provided for decreasing the number of passive elements such as inductance, etc. in microwave oscillators and frequency doublers. A microwave oscillator circuit is connected to a resonator circuit generating a signal at a frequency f, and produces at its output a signal of frequency nf, and comprises a first field effect transistor having a gate connected to the resonator circuit, a second field effect transistor whose source/drain path is connected in series with the source/drain path of the first field effect transistor and a connecting circuit for coupling either the gate or source of the first field effect transistor to the gate of the second field effect transistor. A signal of frequency nf is output at a node corresponding to a connection point between the source of the first field effect transistor and the drain of the second field effect transistor.
    Type: Grant
    Filed: September 16, 1992
    Date of Patent: August 23, 1994
    Assignee: NEC Corporation
    Inventors: Tatsuya Miya, Kazuyoshi Uemura, Sadayoshi Yoshida