Patents by Inventor Sadayuki Jimbo

Sadayuki Jimbo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10020362
    Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of the second conductivity type, and an insulating portion. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The insulating portion is located in a vicinity of, and contacts, the second semiconductor region and the third semiconductor region, and the insulating portion includes a plurality of voids therein, the plurality of voids extending around the second semiconductor region.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: July 10, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masanobu Tsuchitani, Hideki Okumura, Sadayuki Jimbo, Takuya Yamaguchi
  • Patent number: 9865680
    Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type on a first electrode and a second semiconductor region of the first conductivity type on a central portion of the first semiconductor region. The second region has a carrier concentration less than a carrier concentration of the first region. A third semiconductor region of a second conductivity type is on the second semiconductor region. A first insulating portion covers a peripheral surface of the second semiconductor region and a peripheral surface of the third semiconductor region. A second insulating portion is spaced from the first insulating portion in a lateral direction. A void space is between the first and second insulating portions. A third insulating portion is on the third semiconductor region and spans and covers the void space. A second electrode is on the third semiconductor region and the third insulating portion.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: January 9, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideki Okumura, Takuya Yamaguchi, Masanobu Tsuchitani, Sadayuki Jimbo
  • Publication number: 20170263703
    Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type on a first electrode and a second semiconductor region of the first conductivity type on a central portion of the first semiconductor region. The second region has a carrier concentration less than a carrier concentration of the first region. A third semiconductor region of a second conductivity type is on the second semiconductor region. A first insulating portion covers a peripheral surface of the second semiconductor region and a peripheral surface of the third semiconductor region. A second insulating portion is spaced from the first insulating portion in a lateral direction. A void space is between the first and second insulating portions. A third insulating portion is on the third semiconductor region and spans and covers the void space. A second electrode is on the third semiconductor region and the third insulating portion.
    Type: Application
    Filed: August 29, 2016
    Publication date: September 14, 2017
    Inventors: Hideki OKUMURA, Takuya YAMAGUCHI, Masanobu TSUCHITANI, Sadayuki JIMBO
  • Publication number: 20170069714
    Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of the second conductivity type, and an insulating portion. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The insulating portion is located in a vicinity of, and contacts, the second semiconductor region and the third semiconductor region, and the insulating portion includes a plurality of voids therein, the plurality of voids extending around the second semiconductor region.
    Type: Application
    Filed: August 30, 2016
    Publication date: March 9, 2017
    Inventors: Masanobu TSUCHITANI, Hideki OKUMURA, Sadayuki JIMBO, Takuya YAMAGUCHI
  • Patent number: 5756402
    Abstract: A method for etching a silicon nitride film, includes the steps of supplying a fluorine radical, a compound of fluorine and hydrogen, and an oxygen radical close to a substrate having the silicon nitride film, and selectively etching the silicon nitride film from the substrate with the fluorine radical, the compound of fluorine and hydrogen, and the oxygen radical.
    Type: Grant
    Filed: April 24, 1995
    Date of Patent: May 26, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Sadayuki Jimbo, Tokuhisa Ohiwa, Haruki Mori, Akira Kobayashi, Tadashi Shinmura, Yasuyuki Taniguchi
  • Patent number: 5445710
    Abstract: A dry-etching method comprising the steps of forming carbon film on a substrate to be etched, forming a resist pattern on said carbon thin film, selectively etching said carbon film using said resist pattern as a mask by a plasma of a gas mixture of a gas containing fluorine atoms and a gas containing oxygen atoms which are mixed at an atomic ratio of fluorine to oxygen of 198:1 to 1:2 so as to form a carbon film pattern, and selectively etching said substrate to be etched using said carbon film pattern as a mask or said resist pattern and said carbon film pattern as masks.
    Type: Grant
    Filed: February 25, 1994
    Date of Patent: August 29, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Hori, Hiroyuki Yano, Keiji Horioka, Hisataka Hayashi, Sadayuki Jimbo, Haruo Okano, Kazuhiro Tomioka, Yasuhiro Ito, Haruki Mori
  • Patent number: 5302240
    Abstract: A dry-etching method comprising the steps of forming carbon film on a substrate to be etched, forming a resist pattern on said carbon thin film, selectively etching said carbon film using said resist pattern as a mask by a plasma of a gas mixture of a gas containing fluorine atoms and a gas containing oxygen atoms which are mixed at an atomic ratio of fluorine to oxygen of 198:1 to 1:2 so as to form a carbon film pattern, and selectively etching said substrate to be etched using said carbon film pattern as a mask or said resist pattern and said carbon film pattern as masks.
    Type: Grant
    Filed: February 19, 1993
    Date of Patent: April 12, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Hori, Hiroyuki Yano, Keiji Horioka, Hisataka Hayashi, Sadayuki Jimbo, Haruo Okano, Kazuhiro Tomioka, Yasuhiro Ito, Haruki Mori
  • Patent number: 5240554
    Abstract: A method of manufacturing a semiconductor device includes the steps of forming a carbon film on a target film formed on a substrate, forming an organic film pattern on the carbon film, etching the carbon film using the organic film pattern as a mask to form a carbon film pattern, and heating the substrate, supplying an etching gas having halogen atoms to a reaction area where the substrate is stored, applying an electric field to the reaction area to generate a discharge, and anisotropically etching the silicon oxide film using the carbon film pattern as a mask and a plasma formed by the discharge.
    Type: Grant
    Filed: January 22, 1992
    Date of Patent: August 31, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Hori, Hiroyuki Yano, Keiji Horioka, Hisataka Hayashi, Sadayuki Jimbo, Haruo Okano