Patents by Inventor Sadayuki Moroi

Sadayuki Moroi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170309547
    Abstract: A method for manufacturing a semiconductor device includes preparing a lead frame that includes a die pad including a first plane and a second plane located on an opposite side of the first plane, and a plurality of leads arranged next to the die pad, mounting a semiconductor chip including a surface, a plurality of electrodes formed over the surface, and a reverse side located on an opposite side of the surface over a chip mounting area of the first plane of the die pad, electrically coupling parts of the electrodes of the semiconductor chip and the leads through a plurality of first wires and electrically coupling other parts of the electrodes and the die pad through a second wire after the mounting the semiconductor chip, and after the electrically coupling, sealing the semiconductor chip, the first wires, and the second wire with a resin.
    Type: Application
    Filed: July 7, 2017
    Publication date: October 26, 2017
    Inventors: Akito SHIMIZU, Kenji Nishikawa, Sadayuki Moroi, Tomoo Imura
  • Patent number: 9741641
    Abstract: A semiconductor device, includes a die pad that has a first main surface and a second main surface located on the opposite side of the first main surface; a lead arranged next to the die pad; a semiconductor chip that has a surface, a first electrode and a second electrode formed on the surface, and a reverse side located on the opposite side of the surface, and is mounted on a chip mounting area of the first main of the die pad; a first wire that electrically couples the first electrode of the semiconductor chip and the lead; a second wire that electrically couples the second electrode of the semiconductor chip and the die pad; and a sealed body that seals the semiconductor chip, the first wire, and the second wire.
    Type: Grant
    Filed: January 16, 2016
    Date of Patent: August 22, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Akito Shimizu, Kenji Nishikawa, Sadayuki Moroi, Tomoo Imura
  • Publication number: 20160133548
    Abstract: A semiconductor device, includes a die pad that has a first main surface and a second main surface located on the opposite side of the first main surface; a lead arranged next to the die pad; a semiconductor chip that has a surface, a first electrode and a second electrode formed on the surface, and a reverse side located on the opposite side of the surface, and is mounted on a chip mounting area of the first main of the die pad; a first wire that electrically couples the first electrode of the semiconductor chip and the lead; a second wire that electrically couples the second electrode of the semiconductor chip and the die pad; and a sealed body that seals the semiconductor chip, the first wire, and the second wire.
    Type: Application
    Filed: January 16, 2016
    Publication date: May 12, 2016
    Inventors: Akito SHIMIZU, Kenji NISHIKAWA, Sadayuki MOROI, Tomoo lmura
  • Patent number: 9293396
    Abstract: A method for manufacturing a semiconductor device, includes: (a) preparing a lead frame that includes a die pad having a first plane and a second plane located on the opposite side of the first plane, and a plurality of leads arranged next to the die pad; (b) mounting a semiconductor chip having a surface, a plurality of electrodes formed over the surface, and a reverse side located on the opposite side of the surface over a chip mounting area of the first plane of the die pad; (c) electrically coupling parts of the electrodes of the semiconductor chip and the leads through a plurality of first wires and electrically coupling the other parts of the electrodes and the die pad through a second wire.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: March 22, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Akito Shimizu, Kenji Nishikawa, Sadayuki Moroi, Tomoo Imura
  • Publication number: 20150194368
    Abstract: A method for manufacturing a semiconductor device, includes: (a) preparing a lead frame that includes a die pad having a first plane and a second plane located on the opposite side of the first plane, and a plurality of leads arranged next to the die pad; (b) mounting a semiconductor chip having a surface, a plurality of electrodes formed over the surface, and a reverse side located on the opposite side of the surface over a chip mounting area of the first plane of the die pad; (c) electrically coupling parts of the electrodes of the semiconductor chip and the leads through a plurality of first wires and electrically coupling the other parts of the electrodes and the die pad through a second wire.
    Type: Application
    Filed: March 16, 2015
    Publication date: July 9, 2015
    Inventors: Akito SHIMIZU, Kenji Nishikawa, Sadayuki Moroi, Tomoo Imura
  • Patent number: 9018745
    Abstract: A method according to the invention has a bonding process of mounting a semiconductor chip on an upper surface of a die pad that has the upper surface whose area is larger than a reverse side of the semiconductor chip. It also has a sealed body formation process of sealing the semiconductor chip so that an undersurface opposite to the upper surface of the die pad may be exposed after the bonding process. Here, the upper surface of the die pad is arranged around an area over which the semiconductor chip is mounted, and has a hollow part arrangement area in which a groove or multiple holes are formed. Moreover, surface roughness of the upper surface is made coarser than surface roughness of the undersurface.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: April 28, 2015
    Assignee: Renesas Corporation
    Inventors: Akito Shimizu, Kenji Nishikawa, Sadayuki Moroi, Tomoo Imura
  • Publication number: 20140001620
    Abstract: A method according to the invention has a bonding process of mounting a semiconductor chip on an upper surface of a die pad that has the upper surface whose area is larger than a reverse side of the semiconductor chip. It also has a sealed body formation process of sealing the semiconductor chip so that an undersurface opposite to the upper surface of the die pad may be exposed after the bonding process. Here, the upper surface of the die pad is arranged around an area over which the semiconductor chip is mounted, and has a hollow part arrangement area in which a groove or multiple holes are formed. Moreover, surface roughness of the upper surface is made coarser than surface roughness of the undersurface.
    Type: Application
    Filed: May 20, 2013
    Publication date: January 2, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Akito Shimizu, Kenji Nishikawa, Sadayuki Moroi, Tomoo Imura
  • Patent number: 5726490
    Abstract: A leadframe assembly is used in which a ground metal plane (1) having a ground external lead (2), an annular insulating tape (4), a power supply metal plane (5) having a power supply external lead (6), an annular insulating tape (4') and a leadframe (7) having signalling internal and external leads (8, 9) with the ground and power supply external leads removed are sequentially laminated from below. Since each metal plane is provided with a resin sealing dam bar (3) of the same form as that of the leadframe (7), they can be sealed with resin together, and then the resin sealing dam bar (3) is removed and the leads (2, 6, 9) are formed to complete the semiconductor device. Thus, the process for joining the metal planes to the ground and power supply external leads becomes unnecessary, and an inexpensive semiconductor device can be realized.
    Type: Grant
    Filed: September 20, 1995
    Date of Patent: March 10, 1998
    Assignee: NEC Corporation
    Inventor: Sadayuki Moroi