Abstract: A coherent optical reception device includes a local oscillation laser that supplies laser light, a coherent optical reception front-end unit that receives a multi-level modulated optical signal, demodulates the optical signal on the basis of the laser light, and converts a demodulated optical signal into an electrical analog signal, an analog-to-digital converter that converts the analog signal into a digital signal, a compensation unit that compensates for an influence of dispersion due to a wavelength or a polarized wave of the optical signal and recovers a carrier phase of the digital signal, a constellation distortion compensation unit that compensates for constellation distortion of the multi-level modulation included in the digital signal in which an influence of dispersion is compensated for by the compensation unit, and an error correction decoding unit that performs error correction of the digital signal in which the constellation distortion is compensated for.

Abstract: A coherent optical reception device includes a local oscillation laser that supplies laser light, a coherent optical reception front-end unit that receives a multi-level modulated optical signal, demodulates the optical signal on the basis of the laser light, and converts a demodulated optical signal into an electrical analog signal, an analog-to-digital converter that converts the analog signal into a digital signal, a compensation unit that compensates for an influence of dispersion due to a wavelength or a polarized wave of the optical signal and recovers a carrier phase of the digital signal, a constellation distortion compensation unit that compensates for constellation distortion of the multi-level modulation included in the digital signal in which an influence of dispersion is compensated for by the compensation unit, and an error correction decoding unit that performs error correction of the digital signal in which the constellation distortion is compensated for.

Abstract: A write preference determination unit (30A) compares a reception rate of packets received from the lines of a first network (NW1) with a reception rate threshold for write preference determination, and in a case where the reception rate exceeds the reception rate threshold, determines that preference of a write operation is necessary. A write preference control unit (30B) increases, out of a total access bandwidth of a packet buffer (BUF), a write bandwidth for a packet write operation to the packet buffer (BUF) as compared to a read bandwidth for a packet read operation from the packet buffer (BUF) in a case where the write preference determination unit (30A) determines that the preference is necessary, thereby preferentially executing the packet write operation to the packet buffer. This suppresses occurrence of linked discard of reception packets caused by a shortage of the write bandwidth.

Abstract: A packet transfer processing device includes common processing units that perform processing common to inbound processing of a packet received from an access network for transfer to a core network and outbound processing of a packet received from the core network for transfer to the access network, an input destination switching unit that selects common processing units to which the received packets are to be input, an output destination switching unit that outputs packets processed by the common processing units to a destination network, an individual processing switching unit that selects a common processing unit to connect to an individual processing unit that performs individual processing not performed by the common processing units as part of inbound processing, and a control unit that controls the input destination switching unit, the individual processing switching unit, and switching supply/shutoff of power to the common processing units.

Abstract: A write preference determination unit (30A) compares a reception rate of packets received from the lines of a first network (NW1) with a reception rate threshold for write preference determination, and in a case where the reception rate exceeds the reception rate threshold, determines that preference of a write operation is necessary. A write preference control unit (30B) increases, out of a total access bandwidth of a packet buffer (BUF), a write bandwidth for a packet write operation to the packet buffer (BUF) as compared to a read bandwidth for a packet read operation from the packet buffer (BUF) in a case where the write preference determination unit (30A) determines that the preference is necessary, thereby preferentially executing the packet write operation to the packet buffer. This suppresses occurrence of linked discard of reception packets caused by a shortage of the write bandwidth.

Abstract: Out of one constantly fed block (B0) and one power saving block (B1) provided by dividing in advance circuit units constituting an OLT (10), a power supply control unit (40) constantly supplies power to circuit units belonging to the constantly fed block. For circuit units belonging to the power saving block, the power supply control unit starts power supply to the power saving block starts in synchronism with the start of the period of an upstream bandwidth allocated to each ONU, and stops the power supply to the power saving block in synchronism with the end of the period of the upstream bandwidth. The power supply control unit starts power supply at a timing specified based on the start timing of the upstream bandwidth, and stops the power supply at a timing decided based on the end timing of the upstream bandwidth. This reduces the power consumption of an overall OLT.

Abstract: A packet transfer processing device includes a common processing unit (2, 3) that performs processing sharable in inbound processing that receives a packet from an access network and transfers the packet to a core network and outbound processing that receives a packet from the core network and transfers the packet to the access network, an input destination switching unit (5) that selects a common processing unit to which the packets received from the access network and the core network are to be input, an output destination switching unit (6) that outputs the packet processed by the common processing unit (2, 3) to a network of a transfer destination, an individual processing switching unit (7) that selects which common processing unit is to be connected to an individual processing unit (10) that performs first individual processing nonsharable by the common processing unit (2, 3) out of the inbound processing, and a control unit (4) that performs control of the input destination switching unit (5), control

Abstract: When a data signal of a first channel is an RZ signal having a pulse period T1 and a logic “1” pulse width m, a data signal of a second channel is an RZ signal having a pulse period T2 and a logic “1” pulse width n and the relation n<m is satisfied, a multiplexed signal D obtained by time-division multiplexing the data signals of two channels is input. A pulse signal with a pulse width k satisfying n<k<min(m, T2) is generated at timing of a leading edge of the data signal of each channel. When the multiplexed signal D is judged as logic “1” at timing of a trailing edge of the pulse signal, the data signal of the first channel is output. Similarly, when the multiplexed signal D is judged as logic “0”, the data signal of the second channel is output.

Abstract: When a data signal of a first channel is an RZ signal having a pulse period T1 and a logic “1” pulse width m, a data signal of a second channel is an RZ signal having a pulse period T2 and a logic “1” pulse width n and the relation n<m is satisfied, a multiplexed signal D obtained by time-division multiplexing the data signals of two channels is input. A pulse signal with a pulse width k satisfying n<k<min(m, T2) is generated at timing of a leading edge of the data signal of each channel. When the multiplexed signal D is judged as logic “1” at timing of a trailing edge of the pulse signal, the data signal of the first channel is output. Similarly, when the multiplexed signal D is judged as logic “0”, the data signal of the second channel is output.

Abstract: When a data signal of a first channel is an RZ signal having a pulse period T1 and a logic “1” pulse width m, a data signal of a second channel is an RZ signal having a pulse period T2 and a logic “1” pulse width n and the relation n < m is satisfied, a multiplexed signal D obtained by time-division multiplexing the data signals of two channels is input. A pulse signal with a pulse width k satisfying n < k < min(m, T2) is generated at timing of a leading edge of the data signal of each channel. When the multiplexed signal D is judged as logic “1” at timing of a trailing edge of the pulse signal, the data signal of the first channel is output. Similarly, when the multiplexed signal D is judged as logic “0”, the data signal of the second channel is output.

Abstract: When a data signal of a first channel is an RZ signal having a pulse period T1 and a logic “1” pulse width m, a data signal of a second channel is an RZ signal having a pulse period T2 and a logic “1” pulse width n and the relation n<m is satisfied, a multiplexed signal D obtained by time-division multiplexing the data signals of two channels is input. A pulse signal with a pulse width k satisfying n<k<min(m, T2) is generated at timing of a leading edge of the data signal of each channel. When the multiplexed signal D is judged as logic “1” at timing of a trailing edge of the pulse signal, the data signal of the first channel is output. Similarly, when the multiplexed signal D is judged as logic “O”, the data signal of the second channel is output.