Abstract: According to one embodiment, the computing device includes a modeling processing unit configured to model characteristics of selected cell transistor and to define a non-selected cell transistor as a parasitic resistance component of the selected cell transistor. The computing device further includes a computation processing unit configured to use as a parameter a distance between both ends of an active region of the selected cell transistor, and further to store threshold characteristics of the selected cell transistor present in the memory string as a parameter, and to obtain electrical characteristics of the selected cell transistor. The computing device is used for a circuit simulation of a semiconductor memory device including memory string of a plurality of cell transistors connected to one another in series in a channel direction.

Abstract: A circuit simulation apparatus according to an embodiment of the present invention calculates a set value of a SPICE parameter of a MOSFET to carry out a variation analysis on a semiconductor circuit including the MOSFET.

Abstract: In one embodiment, a SPICE corner model generating method for generating a SPICE corner model of an MOSFET includes preparing a table of a ratio X regarding a combination of two kinds of MOSFETs selected from N kinds of MOSFETs, the ratio X being a magnitude of a variation of an MOSFET in a case where directions of variations of the two kinds of MOSFETs are opposite directions to a magnitude of a variation of an MOSFET in a case where the directions of the variations of the two kinds of MOSFETs are the same direction, where N is an integer of 2 or greater. The method further includes reading out, when a combination of two kinds of MOSFETs is designated among the N kinds of MOSFETs, a value of the ratio X corresponding the designated combination from the table of the ratio X.

Abstract: In one embodiment, a MOSFET model output apparatus is configured to output a MOSFET model for a simulation of a semiconductor circuit. The apparatus includes a shape data input part configured to input shape data of a MOSFET. The apparatus further includes a parameter calculation part configured to calculate a parameter of a parasitic device model to be added to the MOSFET model, using the shape data. The apparatus further includes a MOSFET model output part configured to generate and output the MOSFET model added with the parasitic device model, using the parameter of the parasitic device model. Further, the MOSFET model output part adds different parasitic device models to the MOSFET model in a case where the MOSFET is an N-type MOSFET and in a case where the MOSFET is a P-type MOSFET.

Abstract: In one embodiment, a SPICE model parameter output apparatus is configured to output a SPICE model parameter of a high-frequency or analog MOSFET for a simulation of a semiconductor circuit. The apparatus includes a data input part to input shape data of the MOSFET and measurement data on frequency characteristics of the MOSFET. The apparatus further includes a substrate resistance calculating part configured to calculate a substrate resistance of a one-terminal substrate resistance model regarding the MOSFET, based on the measurement data. The apparatus further includes a SPICE model parameter output part configured to calculate the SPICE model parameter, based on the substrate resistance of the one-terminal substrate resistance model and the shape data, to output the calculated SPICE model parameter.

Abstract: In one embodiment, a SPICE corner model generating method for generating a SPICE corner model of an MOSFET includes preparing a table of a ratio X regarding a combination of two kinds of MOSFETs selected from N kinds of MOSFETs, the ratio X being a magnitude of a variation of an MOSFET in a case where directions of variations of the two kinds of MOSFETs are opposite directions to a magnitude of a variation of an MOSFET in a case where the directions of the variations of the two kinds of MOSFETs are the same direction, where N is an integer of 2 or greater. The method further includes reading out, when a combination of two kinds of MOSFETs is designated among the N kinds of MOSFETs, a value of the ratio X corresponding the designated combination from the table of the ratio X.

Abstract: A method of extracting an equivalent circuit of a T-type transmission circuit measures signals of the first and second terminals to obtain S parameters, converts the S parameters into Z parameters to generate a T-type circuit by using the Z parameters, obtains first to third lead line resistors and first to third lead line inductors in the T-type circuit based on the Z parameters corresponding to constants of the T-type circuit, subtracts the Z parameters corresponding to the T-type circuit from the Z parameters corresponding to all of the equivalent circuit to calculate the Z parameters of a ?-type circuit, converts the Z parameters of the ?-type circuit into the Y parameters, and calculates first to third coupling capacitances based on the Y parameters.

Abstract: A circuit simulation apparatus according to an embodiment of the present invention calculates a set value of a SPICE parameter of a MOSFET to carry out a variation analysis on a semiconductor circuit including the MOSFET.

Abstract: A method of extracting an equivalent circuit of a T-type transmission circuit measures signals of the first and second terminals to obtain S parameters, converts the S parameters into Z parameters to generate a T-type circuit by using the Z parameters, obtains first to third lead line resistors and first to third lead line inductors in the T-type circuit based on the Z parameters corresponding to constants of the T-type circuit, subtracts the Z parameters corresponding to the T-type circuit from the Z parameters corresponding to all of the equivalent circuit to calculate the Z parameters of a ?-type circuit, converts the Z parameters of the ?-type circuit into the Y parameters, and calculates first to third coupling capacitances based on the Y parameters.

Abstract: In a bipolar transistor improved to exhibit an excellent high-frequency property by decreasing the width of the intrinsic base with without increasing the base resistance, an emitter region, intrinsic base region and collector region are closely aligned on an insulating layer, and the intrinsic base region and the collector region make a protrusion projecting upward from the substrate surface. The protrusion has a width wider than the width of the intrinsic base region.

Abstract: In a bipolar transistor improved to exhibit an excellent high-frequency property by decreasing the width of the intrinsic base with without increasing the base resistance, an emitter region, intrinsic base region and collector region are closely aligned on an insulating layer, and the intrinsic base region and the collector region make a protrusion projecting upward from the substrate surface. The protrusion has a width wider than the width of the intrinsic base region.

Abstract: In a lateral bipolar transistor, its emitter region, base region, link base region, and so forth, are made in self alignment with side walls of masks by using partly overlapping two mask patterns. Therefore, not relying on the mask alignment accuracy, these regions are made in a precisely controlled positional relation. Thus, the lateral bipolar transistor, thus obtained, is reduced in parasitic resistance of the base and parasitic junction capacitance between the emitter and the base, and alleviated in variance of characteristics caused by fluctuation of the length of a link base region, length of the emitter-base junction and relative positions of the emitter and the collector, and can be manufactured with a high reproducibility.