Patents by Inventor Sadegh Yazdanshenas

Sadegh Yazdanshenas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • EFFICIENT LOGIC BLOCKS ARCHITECTURES FOR DENSE MAPPING OF MULTIPLIERS
    Publication number: 20240028295
    Abstract: An integrated circuit includes a logic block configured to perform multiplication operations. The logic block includes a plurality of lookup tables configured to receive a plurality of inputs and generate a first plurality of outputs. Additionally, the logic block includes adding circuitry configured to receive the first plurality of outputs and generate a second plurality of outputs. Furthermore, the logic block includes circuitry configured to receive a portion of the plurality of inputs, determine one or more partial products, and generate a third plurality of outputs.
    Type: Application
    Filed: September 25, 2023
    Publication date: January 25, 2024
    Inventors: Sadegh Yazdanshenas, Tim Vanderhoek
  • Efficient logic blocks architectures for dense mapping of multipliers
    Patent number: 11768661
    Abstract: An integrated circuit includes a logic block configured to perform multiplication operations. The logic block includes a plurality of lookup tables configured to receive a plurality of inputs and generate a first plurality of outputs. Additionally, the logic block includes adding circuitry configured to receive the first plurality of outputs and generate a second plurality of outputs. Furthermore, the logic block includes circuitry configured to receive a portion of the plurality of inputs, determine one or more partial products, and generate a third plurality of outputs.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: September 26, 2023
    Assignee: Intel Corporation
    Inventors: Sadegh Yazdanshenas, Tim Vanderhoek
  • Freeze And Clear Logic Circuits And Methods For Integrated Circuits
    Publication number: 20220216873
    Abstract: An integrated circuit includes a programmable logic circuit and freeze circuitry coupled to receive a freeze signal and a control signal. The integrated circuit also includes a logic circuit coupled to receive an output signal of the programmable logic circuit. The logic circuit is also coupled to receive an output signal of the freeze circuitry. The freeze circuitry causes an output signal of the logic circuit to be in a predefined logic state in response to the freeze signal being asserted during power-up of the integrated circuit. The integrated circuit also includes clear circuitry that asserts the control signal in response to a clear signal being asserted after the power-up of the integrated circuit. The freeze circuitry causes the output signal of the logic circuit to be in the predefined logic state in response to the control signal being asserted.
    Type: Application
    Filed: March 24, 2022
    Publication date: July 7, 2022
    Applicant: Intel Corporation
    Inventors: Sadegh Yazdanshenas, Jeffrey Chromczak
  • Efficient Logic Blocks Architectures for Dense Mapping of Multipliers
    Publication number: 20210200514
    Abstract: An integrated circuit includes a logic block configured to perform multiplication operations. The logic block includes a plurality of lookup tables configured to receive a plurality of inputs and generate a first plurality of outputs. Additionally, the logic block includes adding circuitry configured to receive the first plurality of outputs and generate a second plurality of outputs. Furthermore, the logic block includes circuitry configured to receive a portion of the plurality of inputs, determine one or more partial products, and generate a third plurality of outputs.
    Type: Application
    Filed: December 27, 2019
    Publication date: July 1, 2021
    Inventors: Sadegh Yazdanshenas, Tim Vanderhoek