Patents by Inventor Sadogopan Srinivasan

Sadogopan Srinivasan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • POWER EFFICIENT PROCESSOR ARCHITECTURE
    Publication number: 20160299558
    Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
    Type: Application
    Filed: April 21, 2016
    Publication date: October 13, 2016
    Inventors: Andrew J. Herdrich, Rameshkumar G. Illikkal, Ravishankar Iyer, Sadogopan Srinivasan, Jaideep Moses, Srihari Makineni
  • POWER EFFICIENT PROCESSOR ARCHITECTURE
    Publication number: 20160299559
    Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
    Type: Application
    Filed: April 21, 2016
    Publication date: October 13, 2016
    Inventors: Andrew J. Herdrich, Rameshkumar G. Illikkal, Ravishankar Iyer, Sadogopan Srinivasan, Jaideep Moses, Srihari Makineni
  • Power efficient processor architecture
    Patent number: 9360927
    Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: June 7, 2016
    Assignee: Intel Corporation
    Inventors: Andrew J. Herdrich, Rameshkumar G. Illikkal, Ravishankar Iyer, Sadogopan Srinivasan, Jaideep Moses, Srihari Makineni
  • POWER EFFICIENT PROCESSOR ARCHITECTURE
    Publication number: 20130262902
    Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
    Type: Application
    Filed: September 6, 2011
    Publication date: October 3, 2013
    Inventors: Andrew J. Herdrich, Rameshkumar G. Illikkal, Ravishankar Iyer, Sadogopan Srinivasan, Jaideep Moses, Srihari Makineni