Abstract: Managing clock-data recovery for a modulated signal from a communication channel comprises: receiving the modulated signal and providing one or more analog signals, providing one or more digital input streams from samples of the analog signals, and processing the digital input streams to provide decoded digital data. The processing comprises: determining the decoded digital data based on information modulated over a plurality of frequency elements associated with the modulated signal, based at least in part on transforms of the digital input streams; a clock signal based on clock recovery from the digital input streams; and determining a clock phase error estimate associated with the determined clock signal based at least in part on a sum that includes different weights multiplied by different respective summands corresponding to different sets of frequency elements.

Abstract: Described herein is a digital phase locked loop (PLL) which includes a phase frequency detector (PFD) outputting a pulse width modulated (PWM) up pulse and a PWM down pulse based on comparison of a reference clock and a feedback clock, a digital integral circuit connected to the PFD, the digital integral circuit outputting a digital control signal based on the PWM up and down pulses, and a controlled oscillator (CO) connected to the digital integral circuit and an output and input of the PFD. The CO receiving the PWM up and down pulses from the PFD and adjusting a frequency of the CO based on the digital control signal and the PWM up and down pulses to generate an output clock. The feedback clock is based on the output clock and the reference clock is aligned with the feedback clock by adjusting the output clock frequency until frequency/phase lock.

Abstract: Described herein are apparatus and methods for a successive approximation register (SAR) analog-to-digital (ADC) based phase-locked loop (PLL) with programmable range. A multi-bit digital phase locked loop includes a multi-bit phase frequency detector configured to output a multi-bit error signal based on a reference clock, a feedback clock sampled using the reference clock, and a threshold voltage, a multi-bit digital low pass filter configured to apply a variable gain to the multi-bit error signal, a current steered digital-to-analog converter configured to generate a control current based on a gain applied multi-bit error signal and multi-bit digital phase locked loop control parameters, a controlled oscillator configured to adjust a frequency of the controlled oscillator based on the control current to generate an output clock, the feedback clock being based on the output clock, and a programmable edge time controller configured to adjust a slope of an edge of the feedback clock.

Abstract: Described herein are apparatus and methods for a high bandwidth under-sampled successive approximation register (SAR) analog to digital converter (ADC) (SAR ADC) with non-linearity minimization. A method includes sampling, by a sampling switch triggered by a sampling clock in the SAR ADC, an input signal, determining, by a comparator in the SAR ADC, a value for a bit based on comparing the sampled input signal to a reference signal provided by a reference digital-to-analog (DAC) in the SAR ADC, wherein the input signal and the reference signal propagate through substantially similar input paths, resampling, by the sampling switch, the input signal for each successive bit, determining, by the comparator, a value for each successive bit based on comparing the resampled input signal and a reference signal for each successive bit, and outputting, by a digital controller, a digital result after determining a value for a last bit by the comparator.

Abstract: Described are apparatus and methods for successive approximation register (SAR) analog to digital converter (ADC) (SAR ADC) with factoring and background clock calibration. An apparatus includes a SAR ADC configured to, in response to receiving an enable flag based on detection of an acquisition clock with a first logic state sent by a controller, sample and convert a pair of differential input signals using a sampling clock to obtain a defined number of samples in an acquisition clock cycle and a factoring circuit configured to obtain the defined number of samples from the SAR ADC using a capturing clock based on the sampling clock, factor the defined number of samples, and send a factored samples ready flag to the controller.

Abstract: Described are apparatus and methods for high frequency clock generation. A circuit includes a phase frequency detector (PFD) which outputs differential error clocks based on comparison of differential reference clocks and differential feedback clocks, which are at a first frequency. A controlled oscillator (CO) connected to the PFD, which adjusts a frequency of the CO based on the differential error clocks to generate differential clocks at a second frequency, which is a multiple of the first frequency. A quadrature clock generator connected to the CO, which generates differential quadrature clocks at the second frequency from the differential clocks, where the differential feedback clocks are generated from the differential clocks and one pair of the differential quadrature clocks. A frequency doubler which doubles each pair of the differential quadrature clocks and outputs fully differential and balanced clocks at a third frequency for distribution, which is a multiple of the second frequency.

Abstract: An optical system includes a transmitter including transmitter circuitry configured to cause transmission of a transmitted optical signal over a fiber link on an X polarization and a Y polarization; and a receiver including receiver circuitry configured to receive a received optical signal from the fiber link on the X polarization and the Y polarization, wherein the transmitter circuitry is configured to cause State of Polarization (SOP) changes on the X polarization and the Y polarization for a test of the fiber link. The transmitter circuitry and the receiver circuitry are built-in with the transmitter and the receiver, respectively, for performance of the test.

Abstract: Techniques and circuits are proposed to increase averaging in the clock recovery band based on an amount of channel overlap in receivers using excess bandwidth for clock recovery, to mitigate the impact of spectral energy leaking into an active channel of interest from an adjacent active channel and to improve the accuracy of the phase estimate of the received transmitted clock.

Abstract: Described is a digital fractional phase locked loop (DFPLL) with a current mode low pass filter. The DFPLL includes a binary phase frequency detector (BPFD) configured to output a directional pulse based on comparison of a reference clock and a feedback clock, a current mode low pass filter connected to the BPFD, and a current controlled oscillator (CCO) connected to the current mode low pass filter. The current mode low pass filter configured to output a control current based on at least the directional pulse when a current steering switch directly controlled by the directional pulse switches to the CCO. The CCO configured to adjust a frequency of the CCO based on the control current to generate an output clock. The feedback clock based on the output clock and the reference clock aligned with the feedback clock by adjusting the frequency of the output clock until frequency and phase lock.

Abstract: A noise-shaping enhanced (NSE) gated ring oscillator (GRO)-based ADC includes a delay which delays and feedbacks an error signal to an input of the NSE GRO-based ADC. The feedback error signal provides an order of noise-shaping and the error signal is generated at the input of the NSE GRO-based ADC from an input signal, the feedback error signal, and a front-end output. A voltage-to-time converter converts the error signal to the time domain. A GRO outputs phase signals from the time domain error signal by oscillating when the error signal is high and inhibiting oscillation otherwise. A quantization device quantizes the phase signals to generate the front-end output. A quantization extraction device determines a quantization error from the quantized phase signals. A time-to-digital converter digitizes the quantization error to generate a back-end output. An output device generates a second order noise-shaped output based on the front-end and the back-end outputs.

Abstract: A system includes an optical transmitter including a transmitter Phase Lock Loop (PLL) circuit; an optical receiver connected to the optical transmitter and including a receiver PLL circuit; and circuitry configured to inject a test stimulus to a clock causing jitter in one of the transmitter PLL circuitry and the receiver PLL circuit, wherein the test stimulus is set for characterizing the jitter tolerance of optical receiver. As well, a circuit that injects SOP transient at the transmitter is included. It is configured to test the tolerance of optical receiver to handle fast change in the SOP state. The optical receiver is configured to determine if the system is operational at a jitter value due to the test stimulus based on compliance to one or more thresholds including any of a target Bit Error Rate, a Forward-Error-Correction (FEC) hit, and a jitter Root Mean Square (RMS).

Abstract: A system includes an optical transmitter including a transmitter Phase Lock Loop (PLL) circuit; an optical receiver connected to the optical transmitter and including a receiver PLL circuit; and circuitry configured to inject a test stimulus to a clock causing jitter in one of the transmitter PLL circuitry and the receiver PLL circuit, wherein the test stimulus is set for characterizing the jitter tolerance of optical receiver. As well, a circuit that injects SOP transient at the transmitter is included. It is configured to test the tolerance of optical receiver to handle fast change in the SOP state. The optical receiver is configured to determine if the system is operational at a jitter value due to the test stimulus based on compliance to one or more thresholds including any of a target Bit Error Rate, a Forward-Error-Correction (FEC) hit, and a jitter Root Mean Square (RMS).

Abstract: Clock circuits, components, systems and signal processing methods enabling digital communication are described. A phase locked loop device derives an output signal locked to a first reference clock signal in a feedback loop. A common phase detector is employed to obtain phase differences between a copy of the output signal and a second reference clock signal. The phase differences are employed in an integral phase control loop within the feedback loop to lock the phase locked loop device to the center frequency of the second reference signal. The phase differences are also employed in a proportional phase control loop within the feedback loop to reduce the effect of imperfect component operation. Cascading the integral and proportional phase control within the feedback loop enables an amount of phase error to be filtered out from the output signal.

Abstract: Clock circuits, components, systems and signal processing methods enabling digital communication are described. A phase locked loop device derives an output signal locked to a first reference clock signal in a feedback loop. A common phase detector is employed to obtain phase differences between a copy of the output signal and a second reference clock signal. The phase differences are employed in an integral phase control loop within the feedback loop to lock the phase locked loop device to the center frequency of the second reference signal. The phase differences are also employed in a proportional phase control loop within the feedback loop to reduce the effect of imperfect component operation. Cascading the integral and proportional phase control within the feedback loop enables an amount of phase error to be filtered out from the output signal.

Abstract: A receiver gain tracking loop utilizing two Digital-to-Analog Converters (DACs) and methods for operating the gain tracking loop are provided. The gain tracking circuit includes a signal detector for detecting at least one signal and outputting a detected signal; a digital integrator connected in series to the signal detector for integrating the detected signal in the digital domain; two DACs connected in parallel to the digital integrator; and an analog summing element for summing the first digital output and the second digital output of the DACs producing a combined output.

Abstract: Described herein is a digital phase locked loop (PLL) which includes a phase frequency detector (PFD) outputting a pulse width modulated (PWM) up pulse and a PWM down pulse based on comparison of a reference clock and a feedback clock, a digital integral circuit connected to the PFD, the digital integral circuit outputting a digital control signal based on the PWM up and down pulses, and a controlled oscillator (CO) connected to the digital integral circuit and an output and input of the PFD. The CO receiving the PWM up and down pulses from the PFD and adjusting a frequency of the CO based on the digital control signal and the PWM up and down pulses to generate an output clock. The feedback clock is based on the output clock and the reference clock is aligned with the feedback clock by adjusting the output clock frequency until frequency/phase lock.

Abstract: Digital jitter accumulation reduction techniques and circuits are proposed to mitigate jitter accumulation in Voltage Controlled Oscillators (VCOs). In order to reduce jitter accumulation, employing a pair of identical injection locked VCOs is proposed in an interleaved fashion. Further jitter accumulation reductions can be provided by employing a plurality of identical injection locked VCOs selected in a cascading fashion. Yet further jitter accumulation reductions can be provided by resetting the deselected VCO(s).

Abstract: A circuit includes a programmable frequency divider which receives a high-speed clock, fin, as an input and which provides a modulated reference clock as an output; a Sigma-Delta modulator which receives a Frequency Control Word (FCW) and which is connected to the programmable frequency divider to receive the modulated reference clock as a sample clock and to control an average frequency of the modulated reference clock; and an integer-N Phase Lock Loop (PLL) which receives the modulated reference clock and outputs a clock output.

Abstract: A decision feedback equalizer (DFE) comprises four charge-steering (CS) primary latches and four primary taps. Two of the four CS primary latches are driven by complementary in-phase quarter-rate clocks and the other two of the four CS primary latches are driven by complementary quadrature quarter-rate clocks. No element of the DFE is driven by any half-rate clocks. In some implementations, each of the primary latches including a respective differential pair of n-channel output transistors and each primary tap includes a respective differential pair of p-channel input transistors connected via their gate nodes to a respective one of the four CS primary latches. In other implementations, each of the primary latches including a respective differential pair of p-channel input transistors and each primary tap includes a respective differential pair of n-channel output transistors connected via their gate nodes to a respective one of the four CS primary latches.

Abstract: A decision feedback equalizer (DFE) comprises two charge-steering (CS) input latches driven by complementary ½-rate clocks, two pairs of CS primary latches, and two pairs of taps. The primary latches are driven by ¼-rate clocks. In a first aspect, each one of the input latches and the primary latches includes a respective differential pair of n-channel output transistors, and each tap includes a respective differential pair of p-channel input transistors. In a second aspect, each one of the input latches and the primary latches includes a respective differential pair of p-channel input transistors, and each tap includes a respective differential pair of n-channel output transistors. In some implementations, no element of any one of the taps is driven by any ½-rate clock. In some implementations, every switch of at least one of the taps is driven by one of the ¼-rate clocks.