Abstract: A phase locked loop (PLL) circuit adjusts a voltage controlled differential oscillator to generate an output frequency signal, which is a selected multiple of an input reference signal. The PLL circuit includes an oscillator control circuit for increasing and decreasing the PLL output frequency signal, a frequency detector for detecting a phase shift between the reference signal and the PLL output signal and produces an error signal, and a fast lock circuit for detecting when the output frequency signal passes the selected multiple of the reference signal. This circuit design provides improved jitter performance, tolerates process variation, and extends the PLL operating frequency range.

Abstract: An analog to digital converter having a group of subrange analysis blocks and reference voltage and offset voltage selection blocks. Each subrange analyses block produces an output representative of a range of bits in a digital output of the analog digital converter. The reference voltage and offset voltage selection blocks enable the operating conditions for the next subrange analysis block to be optimized for both linearity and operating speed.