Patents by Inventor Saeed Fouladi Fard

Saeed Fouladi Fard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11687365
    Abstract: A computational storage processor (CSP) is provided that includes the CSP comprising a plurality of submission queues (SQs), a plurality of computational storage functions (CSFs), a CSF controller, and a CSP controller, and a method of controlling the CSP is provided that includes directing a first submission queue entry (SQE) that is written to a first one of the plurality of SQs to the CSF controller, generating, by the CSF controller, one or more secondary SQEs based on the first SQE, each of the one or more secondary SQEs is directed to a respective one of the CSFs, writing, by the CSF controller, the one or more secondary SQEs to a second one of the plurality of SQs, directing each of the one or more secondary SQEs to an associated respective one of the CSFs, and for each of the one or more secondary SQEs, performing, by the associated respective one of the CSFs, an operation associated with the secondary SQE.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: June 27, 2023
    Assignee: EIDETIC COMMUNICATIONS INC.
    Inventors: Sean Gregory Gibb, Saeed Fouladi Fard
  • Publication number: 20230060654
    Abstract: Systems and methods are provided for mitigating effects of hash collisions in hardware data compression, for example reducing or avoiding the side effects of hash collisions, or reducing or avoiding slow downs caused by hash collisions. In an aspect, a processor-implemented method includes: hashing an input data byte sequence to produce a hash value, the input data byte sequence being located at a sequence address within an input data stream; and storing, in a hash table at a hash address corresponding to the hash value, the sequence address and a portion of the input data byte sequence. In an aspect, to further avoid hash collisions, hash memory accesses are distributed among a plurality of parallel hash banks to increase the throughput. Another aspect virtually extends a hash depth by extending a data match search around broken hash links, going backward in the data sequence.
    Type: Application
    Filed: September 2, 2021
    Publication date: March 2, 2023
    Inventors: Saeed Fouladi Fard, Sean Gibb
  • Patent number: 11468177
    Abstract: A system and method that utilize an encryption engine endpoint to encrypt data in a data storage system are disclosed. In the system and method, the client controls the encryption keys utilized to encrypt and decrypt data such that the encryption keys are not stored together with the encrypted data. Therefore, once data is encrypted, neither the host of the data storage system, nor the encryption engine endpoint have access to the encryption keys required to decrypt the data, which increases the security of the encrypted data in the event of, for example, the data storage system being accessed by an unauthorized party.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: October 11, 2022
    Assignee: Eidetic Communications Inc.
    Inventors: Stephen Bates, Saeed Fouladi Fard
  • Publication number: 20220207158
    Abstract: A system and method that utilize an encryption engine endpoint to encrypt data in a data storage system are disclosed. In the system and method, the client controls the encryption keys utilized to encrypt and decrypt data such that the encryption keys are not stored together with the encrypted data. Therefore, once data is encrypted, neither the host of the data storage system, nor the encryption engine endpoint have access to the encryption keys required to decrypt the data, which increases the security of the encrypted data in the event of, for example, the data storage system being accessed by an unauthorized party.
    Type: Application
    Filed: March 21, 2022
    Publication date: June 30, 2022
    Inventors: Stephen BATES, Saeed FOULADI FARD
  • Patent number: 11372714
    Abstract: A method and a hardware accelerator device are provided for performing erasure coding on the hardware accelerator device that includes a dedicated buffer memory that is resident on the hardware accelerator device and that is connected to a second device via a bus, the method includes receiving, at the dedicated buffer memory, write data directly from the second device via the bus such that receiving the data at the dedicated buffer memory bypasses a buffer memory connected to a central processing unit (CPU), performing, at the hardware accelerator, an erasure coding operation on the write data received at the dedicated buffer memory to generate parity data based on the received write data, transmitting the parity data directly to a storage device connected to the hardware accelerator device via the bus such that transmitting the parity data bypasses the buffer memory connected to the CPU.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: June 28, 2022
    Assignee: EIDETIC COMMUNICATIONS INC.
    Inventors: Stephen Bates, Saeed Fouladi Fard
  • Publication number: 20220197704
    Abstract: A computational storage processor (CSP) is provided that includes the CSP comprising a plurality of submission queues (SQs), a plurality of computational storage functions (CSFs), a CSF controller, and a CSP controller, and a method of controlling the CSP is provided that includes directing a first submission queue entry (SQE) that is written to a first one of the plurality of SQs to the CSF controller, generating, by the CSF controller, one or more secondary SQEs based on the first SQE, each of the one or more secondary SQEs is directed to a respective one of the CSFs, writing, by the CSF controller, the one or more secondary SQEs to a second one of the plurality of SQs, directing each of the one or more secondary SQEs to an associated respective one of the CSFs, and for each of the one or more secondary SQEs, performing, by the associated respective one of the CSFs, an operation associated with the secondary SQE.
    Type: Application
    Filed: December 21, 2020
    Publication date: June 23, 2022
    Inventors: Sean Gregory GIBB, Saeed FOULADI FARD
  • Patent number: 11231868
    Abstract: A method, a hardware accelerator, and a system for performing computational storage utilizing a hardware accelerator device that includes a dedicated buffer memory residing on the hardware accelerator device and is connected to a central processing unit (CPU) via a bus includes receiving, at the hardware accelerator device, computation data from the CPU computing device via the bus, performing, at the hardware accelerator device, a check pointing operation on the received computation data to generate check point data, storing the generated check point data on the dedicated buffer memory residing on the hardware accelerator device, and transmitting the check point data directly from the dedicated buffer memory to a solid state memory connected to the hardware accelerator device via the bus for storage, wherein transmitting the check point data bypasses the CPU.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: January 25, 2022
    Assignee: EIDETIC COMMUNICATIONS INC.
    Inventors: Stephen Bates, Saeed Fouladi Fard
  • Publication number: 20210311633
    Abstract: A method, a hardware accelerator, and a system for performing computational storage utilizing a hardware accelerator device that includes a dedicated buffer memory residing on the hardware accelerator device and is connected to a central processing unit (CPU) via a bus includes receiving, at the hardware accelerator device, computation data from the CPU computing device via the bus, performing, at the hardware accelerator device, a check pointing operation on the received computation data to generate check point data, storing the generated check point data on the dedicated buffer memory residing on the hardware accelerator device, and transmitting the check point data directly from the dedicated buffer memory to a solid state memory connected to the hardware accelerator device via the bus for storage, wherein transmitting the check point data bypasses the CPU.
    Type: Application
    Filed: April 7, 2020
    Publication date: October 7, 2021
    Inventors: Stephen Bates, Saeed Fouladi Fard
  • Publication number: 20210271547
    Abstract: A method and a hardware accelerator device are provided for performing erasure coding on the hardware accelerator device that includes a dedicated buffer memory that is resident on the hardware accelerator device and that is connected to a second device via a bus, the method includes receiving, at the dedicated buffer memory, write data directly from the second device via the bus such that receiving the data at the dedicated buffer memory bypasses a buffer memory connected to a central processing unit (CPU), performing, at the hardware accelerator, an erasure coding operation on the write data received at the dedicated buffer memory to generate parity data based on the received write data, transmitting the parity data directly to a storage device connected to the hardware accelerator device via the bus such that transmitting the parity data bypasses the buffer memory connected to the CPU.
    Type: Application
    Filed: February 27, 2020
    Publication date: September 2, 2021
    Inventors: Stephen BATES, Saeed Fouladi FARD
  • Publication number: 20200210597
    Abstract: A system and method that utilize an encryption engine endpoint to encrypt data in a data storage system are disclosed. In the system and method, the client controls the encryption keys utilized to encrypt and decrypt data such that the encryption keys are not stored together with the encrypted data. Therefore, once data is encrypted, neither the host of the data storage system, nor the encryption engine endpoint have access to the encryption keys required to decrypt the data, which increases the security of the encrypted data in the event of, for example, the data storage system being accessed by an unauthorized party.
    Type: Application
    Filed: December 13, 2019
    Publication date: July 2, 2020
    Applicant: Eidetic Communications Inc.
    Inventors: Stephen BATES, Saeed FOULADI FARD
  • Patent number: 10700713
    Abstract: A method and system are provided for error correction. After row encoding and column encoding, additional codeword data (ACD) and modified parity (P?) may be concurrently created, for each of a plurality of modified column codewords (CCW?), by multiplying initial calculated parity P by a generator matrix G. Each CCW? may include an ACD portion and a P? portion such that each bit in the P? portion of a selected CCW? is present in the ACD portion for one of the other CCW?. In contrast to known approaches, the method and system may provide modified column codewords such that all data and parity bits are present in two codewords while using only two types of codewords, and without using extra parity-on-parity bits. In a set of modified column codewords, each bit in the modified parity in one modified codeword is present in another codeword.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: June 30, 2020
    Assignee: MICROSEMI STORAGE SOLUTIONS, INC.
    Inventors: Peter Graumann, Saeed Fouladi Fard
  • Patent number: 10236915
    Abstract: A system for implementing variable T BCH encoders includes: a polynomial multiplier for multiplying a message polynomial by a difference polynomial to achieve a first value, wherein the message polynomial comprises data bits as coefficients and the difference polynomial comprises minimal polynomials that are present in a T error correcting code and are absent from a T??T error correcting BCH code; a shifter/zero-padder coupled with the BCH encoder, the shifter/zero-padder for multiplying the first value by xN-{tilde over (K)} to achieve a second value; a BCH encoder coupled with the polynomial multiplier, the BCH encoder for dividing the second value by a generator polynomial of the T error correcting BCH code and calculating a remainder based on the dividing to achieve a third value; and a polynomial divider for dividing the third value by the difference polynomial to achieve a fourth value comprising parity of the T??T error correcting BCH code.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: March 19, 2019
    Assignee: Microsemi Solutions (U.S.), Inc.
    Inventors: Peter John Waldemar Graumann, Saeed Fouladi Fard
  • Publication number: 20190044539
    Abstract: A method and system are provided for error correction. In an implementation, after row encoding and column encoding, additional codeword data (ACD) and modified parity (P?) are concurrently created, for each of a plurality of modified column codewords (CCW), by multiplying initial calculated parity P by a generator matrix G. In an example implementation, each CCW? includes an ACD portion and a P? portion such that each bit in the P? portion of a selected CCW is present in the ACD portion for one of the other CCW?. In contrast to known approaches, in an implementation the method and system described herein provide modified column codewords such that all data and parity bits are present in two codewords while using only two types of codewords, and without using extra parity-on-parity bits. In a set of modified column codewords generated according to the method and system described herein, each bit in the modified parity in one modified codeword is present in another codeword.
    Type: Application
    Filed: July 24, 2018
    Publication date: February 7, 2019
    Inventors: Peter GRAUMANN, Saeed Fouladi FARD
  • Publication number: 20180034483
    Abstract: A system for implementing variable T BCH encoders includes: a polynomial multiplier for multiplying a message polynomial by a difference polynomial to achieve a first value, wherein the message polynomial comprises data bits as coefficients and the difference polynomial comprises minimal polynomials that are present in a T error correcting code and are absent from a T??T error correcting BCH code; a shifter/zero-padder coupled with the BCH encoder, the shifter/zero-padder for multiplying the first value by xN?{tilde over (K)} to achieve a second value; a BCH encoder coupled with the polynomial multiplier, the BCH encoder for dividing the second value by a generator polynomial of the T error correcting BCH code and calculating a remainder based on the dividing to achieve a third value; and a polynomial divider for dividing the third value by the difference polynomial to achieve a fourth value comprising parity of the T??T error correcting BCH code.
    Type: Application
    Filed: July 21, 2017
    Publication date: February 1, 2018
    Applicant: Microsemi Solutions (U.S.), Inc.
    Inventors: Peter John Waldemar Graumann, Saeed Fouladi Fard
  • Publication number: 20110113082
    Abstract: Signal filtering and filter design techniques are disclosed. An interconnection circuit switchably couples an input and an output of an element that is operable to perform a signal filtering operation on a signal received at the input so as to provide a filtered signal at the output. This enables the element to be used to implement a series of cascaded signal filtering operations. An iterative filter design method and a data structure that enables control of the element and/or the interconnection circuit are also disclosed. According to another aspect of the invention, an element is operable to perform any of multiple signal filtering operations on a received input signal. Controlled selection of respective sets of filter parameters associated with the multiple signal filtering operations enables the element to be used to implement the signal filtering operations in parallel filtering paths.
    Type: Application
    Filed: February 7, 2008
    Publication date: May 12, 2011
    Inventors: Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce Fordyce Cockburn, Christian Schlegel