Patents by Inventor Saeed KHAROUF

Saeed KHAROUF has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS OF A MATRIX OPERATIONS ACCELERATOR
    Publication number: 20240078283
    Abstract: Systems, methods, and apparatuses relating to a matrix operations accelerator are described.
    Type: Application
    Filed: July 27, 2023
    Publication date: March 7, 2024
    Inventors: Amit GRADSTEIN, Simon RUBANOVICH, Sagi MELLER, Saeed KHAROUF, Gavri BERGER, Zeev SPERBER, Jose YALLOUZ, Ron SCHNEIDER
  • Apparatuses, methods, and systems for instructions of a matrix operations accelerator
    Patent number: 11714875
    Abstract: Systems, methods, and apparatuses relating to a matrix operations accelerator are described.
    Type: Grant
    Filed: December 28, 2019
    Date of Patent: August 1, 2023
    Assignee: Intel Corporation
    Inventors: Amit Gradstein, Simon Rubanovich, Sagi Meller, Saeed Kharouf, Gavri Berger, Zeev Sperber, Jose Yallouz, Ron Schneider
  • Accelerator systems and methods for matrix operations
    Patent number: 10942738
    Abstract: The present disclosure is directed to systems and methods for performing one or more operations on a two dimensional tile register using an accelerator that includes a tiled matrix multiplication unit (TMU). The processor circuitry includes reservation station (RS) circuitry to communicatively couple the processor circuitry to the TMU. The RS circuitry coordinates the operations performed by the TMU. TMU dispatch queue (TDQ) circuitry in the TMU maintains the operations received from the RS circuitry in the order that the operations are received from the RS circuitry. Since the duration of each operation is not known prior to execution by the TMU, the RS circuitry maintains shadow dispatch queue (RS-TDQ) circuitry that mirrors the operations in the TDQ circuitry.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: March 9, 2021
    Assignee: Intel Corporation
    Inventors: Zeev Sperber, Amit Gradstein, Simon Rubanovich, Igor Yanover, Gavri Berger, Eyal Hadas, Saeed Kharouf, Ron Schneider, Sagi Meller, Jose Yallouz
  • ACCELERATOR SYSTEMS AND METHODS FOR MATRIX OPERATIONS
    Publication number: 20200310794
    Abstract: The present disclosure is directed to systems and methods for performing one or more operations on a two dimensional tile register using an accelerator that includes a tiled matrix multiplication unit (TMU). The processor circuitry includes reservation station (RS) circuitry to communicatively couple the processor circuitry to the TMU. The RS circuitry coordinates the operations performed by the TMU. TMU dispatch queue (TDQ) circuitry in the TMU maintains the operations received from the RS circuitry in the order that the operations are received from the RS circuitry. Since the duration of each operation is not known prior to execution by the TMU, the RS circuitry maintains shadow dispatch queue (RS-TDQ) circuitry that mirrors the operations in the TDQ circuitry.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 1, 2020
    Applicant: Intel Corporation
    Inventors: ZEEV SPERBER, Amit Gradstein, Simon Rubanovich, Igor Yanover, Gavri Berger, Eyal Hadas, Saeed Kharouf, Ron Schneider, Sagi Meller, Jose Yallouz
  • APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS OF A MATRIX OPERATIONS ACCELERATOR
    Publication number: 20200201932
    Abstract: Systems, methods, and apparatuses relating to a matrix operations accelerator are described.
    Type: Application
    Filed: December 28, 2019
    Publication date: June 25, 2020
    Inventors: Amit GRADSTEIN, Simon RUBANOVICH, Sagi MELLER, Saeed KHAROUF, Gavri BERGER, Zeev SPERBER, Jose YALLOUZ, Ron SCHNEIDER