Patents by Inventor Saeed Sharifi Tehrani

Saeed Sharifi Tehrani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190213218
    Abstract: The present disclosure includes apparatuses and methods for proactive corrective actions in memory based on a probabilistic data structure. A number of embodiments include a memory, and circuitry configured to input information associated with a subset of data stored in the memory into a probabilistic data structure and proactively determine, at least partially using the probabilistic data structure, whether to take a corrective action on the subset of data stored in the memory.
    Type: Application
    Filed: March 18, 2019
    Publication date: July 11, 2019
    Inventors: Saeed Sharifi Tehrani, Sivagnanam Parthasarathy
  • Publication number: 20190146866
    Abstract: The present disclosure includes apparatuses and methods related to updating reliability data. A number of methods can include receiving, at a variable node, either a first reliability data value with a first hard data value or a second reliability data value with a second hard data value, sending the first hard data value or the second hard data value to each check node coupled to the variable node according to a parity check code, and updating the reliability data based on input from less than all of the check nodes.
    Type: Application
    Filed: January 10, 2019
    Publication date: May 16, 2019
    Inventors: Saeed Sharifi Tehrani, Nicholas J. Richardson
  • Patent number: 10275541
    Abstract: The present disclosure includes apparatuses and methods for proactive corrective actions in memory based on a probabilistic data structure. A number of embodiments include a memory, and circuitry configured to input information associated with a subset of data stored in the memory into a probabilistic data structure and proactively determine, at least partially using the probabilistic data structure, whether to take a corrective action on the subset of data stored in the memory.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: April 30, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Saeed Sharifi Tehrani, Sivagnanam Parthasarathy
  • Patent number: 10241851
    Abstract: Some embodiments include apparatuses and methods using a low-density parity-check (LDPC) decoding circuit to receive information retrieved from memory cells, the information including codewords, and a calculating circuit to calculate a rate of codeword errors in the codewords. The calculation is based on a rate of erroneous bits in the information and a rate of erroneous bits with a selected reliability level. The erroneous bits with the selected reliability level form a portion of the erroneous bits in the information.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: March 26, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Saeed Sharifi Tehrani
  • Patent number: 10191804
    Abstract: The present disclosure includes apparatuses and methods related to updating reliability data. A number of methods can include receiving, at a variable node, either a first reliability data value with a first hard data value or a second reliability data value with a second hard data value, sending the first hard data value or the second hard data value to each check node coupled to the variable node according to a parity check code, and updating the reliability data based on input from less than all of the check nodes.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: January 29, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Saeed Sharifi Tehrani, Nicholas J. Richardson
  • Publication number: 20180039535
    Abstract: The present disclosure includes apparatuses and methods for proactive corrective actions in memory based on a probabilistic data structure. A number of embodiments include a memory, and circuitry configured to input information associated with a subset of data stored in the memory into a probabilistic data structure and proactively determine, at least partially using the probabilistic data structure, whether to take a corrective action on the subset of data stored in the memory.
    Type: Application
    Filed: August 5, 2016
    Publication date: February 8, 2018
    Inventors: Saeed Sharifi Tehrani, Sivagnanam Parthasarathy
  • Publication number: 20170199775
    Abstract: Some embodiments include apparatuses and methods using a low-density parity-check (LDPC) decoding circuit to receive information retrieved from memory cells, the information including codewords, and a calculating circuit to calculate a rate of codeword errors in the codewords. The calculation is based on a rate of erroneous bits in the information and a rate of erroneous bits with a selected reliability level. The erroneous bits with the selected reliability level form a portion of the erroneous bits in the information.
    Type: Application
    Filed: January 11, 2016
    Publication date: July 13, 2017
    Inventor: Saeed Sharifi Tehrani
  • Patent number: 9612903
    Abstract: The present disclosure includes apparatuses and methods related to updating reliability data. A number of methods can include receiving, at a variable node, either a first reliability data value with a first hard data value or a second reliability data value with a second hard data value, sending the first hard data value or the second hard data value to each check node coupled to the variable node according to a parity check code, and updating the reliability data based on input from less than all of the check nodes.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: April 4, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Saeed Sharifi Tehrani, Nicholas J. Richardson
  • Publication number: 20160259686
    Abstract: The present disclosure includes apparatuses and methods related to updating reliability data. A number of methods can include receiving, at a variable node, either a first reliability data value with a first hard data value or a second reliability data value with a second hard data value, sending the first hard data value or the second hard data value to each check node coupled to the variable node according to a parity check code, and updating the reliability data based on input from less than all of the check nodes.
    Type: Application
    Filed: May 17, 2016
    Publication date: September 8, 2016
    Inventors: Saeed Sharifi Tehrani, Nicholas J. Richardson
  • Patent number: 9100153
    Abstract: A method for iteratively decoding a set of encoded samples received from a transmission channel is provided. A data signal indicative of a noise level of the transmission channel is received. A scaling factor is then determined in dependence upon the data signal and the encoded samples are scaled using the scaling factor. The scaled encoded samples are then iteratively decoded. Furthermore, a method for initializing edge memories is provided. During an initialization phase initialization symbols are received from a node of a logic circuitry and stored in a respective edge memory. The initialization phase is terminated when the received symbols occupy a predetermined portion of the edge memory. An iterative process is executed using the logic circuitry storing output symbols received from the node in the edge memory and a symbol is retrieved from the edge memory and provided as output symbol of the node. Yet further an architecture for a high degree variable node is provided.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: August 4, 2015
    Assignee: THE ROYAL INSTITUTION FOR THE ADVANCEMENT OF LEARNING/MCGILL UNIVERSITY
    Inventors: Warren J. Gross, Shie Mannor, Saeed Sharifi Tehrani
  • Publication number: 20140108883
    Abstract: The present disclosure includes apparatuses and methods related to updating reliability data. A number of methods can include receiving, at a variable node, either a first reliability data value with a first hard data value or a second reliability data value with a second hard data value, sending the first hard data value or the second hard data value to each check node coupled to the variable node according to a parity check code, and updating the reliability data based on input from less than all of the check nodes.
    Type: Application
    Filed: October 11, 2012
    Publication date: April 17, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Saeed Sharifi Tehrani, Nicholas J. Richardson
  • Patent number: 8095860
    Abstract: The present invention relates to a decoding method and system for stochastic decoding of linear block codes with parity check matrix. Each encoded sample of a set of encoded samples is converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of digital symbols. Each probability message is then provided to a respective node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear block code. Using the logic circuitry each probability message is processed for determining an estimated sequence of information symbols. If an equality node is in a hold state a chosen symbol is provided from a corresponding memory which is updated by storing output symbols from the equality node when the same is in a state other than a hold state.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: January 10, 2012
    Assignee: The Royal Institution for the Advancement of Learning/McGill University
    Inventors: Warren J. Gross, Shie Mannor, Saeed Sharifi Tehrani
  • Publication number: 20110293045
    Abstract: A method for iteratively decoding a set of encoded samples received from a transmission channel is provided. A data signal indicative of a noise level of the transmission channel is received. A scaling factor is then determined in dependence upon the data signal and the encoded samples are scaled using the scaling factor. The scaled encoded samples are then iteratively decoded. Furthermore, a method for initializing edge memories is provided. During an initialization phase initialization symbols are received from a node of a logic circuitry and stored in a respective edge memory. The initialization phase is terminated when the received symbols occupy a predetermined portion of the edge memory. An iterative process is executed using the logic circuitry storing output symbols received from the node in the edge memory and a symbol is retrieved from the edge memory and provided as output symbol of the node. Yet further an architecture for a high degree variable node is provided.
    Type: Application
    Filed: June 1, 2011
    Publication date: December 1, 2011
    Applicant: The Royal Institution for the advancement of Learning/McGill University
    Inventors: Warren J. Gross, Shie Mannor, Saeed Sharifi Tehrani
  • Publication number: 20100074381
    Abstract: A method for iteratively decoding a set of encoded samples received from a transmission channel is provided. A data signal indicative of a noise level of the transmission channel is received. A scaling factor is then determined in dependence upon the data signal and the encoded samples are scaled using the scaling factor. The scaled encoded samples are then iteratively decoded. Furthermore, a method for initializing edge memories is provided. During an initialization phase initialization symbols are received from a node of a logic circuitry and stored in a respective edge memory. The initialization phase is terminated when the received symbols occupy a predetermined portion of the edge memory. An iterative process is executed using the logic circuitry storing output symbols received from the node in the edge memory and a symbol is retrieved from the edge memory and provided as output symbol of the node. Yet further an architecture for a high degree variable node is provided.
    Type: Application
    Filed: September 25, 2009
    Publication date: March 25, 2010
    Applicant: The Royal Institution for the Advancement of Learning/ McGill University
    Inventors: Warren GROSS, Shie MANNOR, Saeed SHARIFI TEHRANI
  • Publication number: 20090100313
    Abstract: Disclosed is a pipelined iterative process and system. Data is received at an input port and is processed in a symbolwise fashion. Processing of each symbol is performed other than relying on completing the processing of an immediately preceding symbol such that operation of the system or process is independent of an order of the input symbols.
    Type: Application
    Filed: October 14, 2008
    Publication date: April 16, 2009
    Applicant: The Royal Institution for the Advancement of Learning/McGill University
    Inventors: Warren J. GROSS, Shie MANNOR, Saeed SHARIFI TEHRANI
  • Publication number: 20080294970
    Abstract: The present invention relates to a decoding method and system for stochastic decoding of linear block codes with parity check matrix. Each encoded sample of a set of encoded samples is converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of digital symbols. Each probability message is then provided to a respective node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear block code. Using the logic circuitry each probability message is processed for determining an estimated sequence of information symbols. If an equality node is in a hold state a chosen symbol is provided from a corresponding memory which is updated by storing output symbols from the equality node when the same is in a state other than a hold state.
    Type: Application
    Filed: May 23, 2008
    Publication date: November 27, 2008
    Applicant: The Royal Institution for the Advancement of Learning/McGill University
    Inventors: Warren J. Gross, Shie Mannor, Saeed Sharifi Tehrani